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diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn
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@@ -431,9 +431,9 @@ See [[HDL_workflow/coriolis2]] page, for those people doing layout work.
 
 ## Chips4Makers JTAG
 
-As this is an actual ASIC, we do not rely on an FPGA's JTAG TAP interface, instead require a full complete independent implementation of JTAG. Staf Verhaegen has one, with a full test suite, and it is superb and well-written.
+As this is an actual ASIC, we do not rely on an FPGA's JTAG TAP interface, instead require a full complete independent implementation of JTAG. Staf Verhaegen has one, with a full test suite, and it is superb and well-written.  The Libre-SOC version includes DMI (Debug Memory Interface):
 
-    git clone https://gitlab.com/Chips4Makers/c4m-jtag.git
+    git clone https://git.libre-soc.org/c4m-jtag.git
 
 Included is an IDCODE tap point, Wishbone Master (for direct memory read and write, fully independent of the core), IOPad redirection and testing, and general purpose shift register capability for any custom use.