-__pycache__
-*.pyc
-*.egg-info
-*.vcd
-outgoing
+# Byte-compiled / optimized / DLL files
+__pycache__/
+*.py[cod]
+*$py.class
+
+# C extensions
+*.so
+
+# Distribution / packaging
+.Python
+env/
+build/
+develop-eggs/
+dist/
+downloads/
+eggs/
+.eggs/
+lib/
+lib64/
+parts/
+sdist/
+var/
+*.egg-info/
+.installed.cfg
+*.egg
+
+# PyInstaller
+# Usually these files are written by a python script from a template
+# before PyInstaller builds the exe, so as to inject date/other infos into it.
+*.manifest
+*.spec
+
+# Installer logs
+pip-log.txt
+pip-delete-this-directory.txt
+
+# Unit test / coverage reports
+htmlcov/
+.tox/
+.coverage
+.coverage.*
+.cache
+nosetests.xml
+coverage.xml
+*,cover
+.hypothesis/
+
+# Translations
+*.mo
+*.pot
+
+# Django stuff:
+*.log
+local_settings.py
+
+# Flask stuff:
+instance/
+.webassets-cache
+
+# Scrapy stuff:
+.scrapy
+
+# Sphinx documentation
+docs/_build/
+
+# PyBuilder
+target/
+
+# IPython Notebook
+.ipynb_checkpoints
+
+# pyenv
+.python-version
+
+# celery beat schedule file
+celerybeat-schedule
+
+# dotenv
+.env
+
+# virtualenv
+venv/
+ENV/
+
+# Spyder project settings
+.spyderproject
+
+# Rope project settings
+.ropeproject
Migen inside
Build your hardware, easily!
- Copyright 2012-2018 Enjoy-Digital
+ Copyright 2012-2018 / EnjoyDigital
[> Intro
--------
-LiteX is an alternative to Migen/MiSoC maintained and used by Enjoy-Digital
-to build our cores, integrate them in complete SoC and load/flash them to
-the hardware and experiment new features.
-
-The structure of LiteX is kept close to Migen/MiSoC to ease collaboration
-between projects and efforts are made to keep cores developed with LiteX
-compatible with Migen/MiSoC.
-
-[> License
-----------
-LiteX is Copyright (c) 2012-2017 Enjoy-Digital under BSD Lisense.
-Since it is based on Migen/MiSoC, please also refer to LICENSE file in gen/soc
-directory or git history to get correct copyrights.
+LiteX is an alternative to MiSoC maintained and used by Enjoy-Digital to build
+our cores, integrate them in complete SoC and load/flash them to the hardware
+and experiment new features.
+
+ +---------------+
+ |FPGA toolchains|
+ +----^-----+----+
+ | |
+ +--+-----v--+
+ +-------+ | |
+ | Migen +--------> |
+ +-------+ | | Your design
+ | LiteX +---> ready to be used!
+ | |
++----------------------+ | |
+|LiteX Cores Ecosystem +--> |
++----------------------+ +-^-------^-+
+ (Eth,,SATA,,DRAM,,USB, | |
+ PCIe,Video,etc...) + +
+ board target
+ file file
+
+
+The structure of LiteX is kept close to MiSoC to ease collaboration between
+projects.
[> Sub-packages
---------------
gen:
Provides specific or experimental modules to generate HDL that are not integrated
- in Migen.
+ in Migen. (For now a full copy of Migen is included in gen, aim is is to only
+ keep specific or experimental modules)
build:
Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
from setuptools import find_packages
-if sys.version_info[:3] < (3, 3):
- raise SystemExit("You need Python 3.3+")
+if sys.version_info[:3] < (3, 5):
+ raise SystemExit("You need Python 3.5+")
setup(
classifiers=[
"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
"Environment :: Console",
- "Development Status :: Beta",
+ "Development Status :: Alpha",
"Intended Audience :: Developers",
"License :: OSI Approved :: BSD License",
"Operating System :: OS Independent",