power: Add support for real-mode addressing (translation is off)

This patch adds support for executing programs which don't have the
translation support (MSR[IR, DR] = 0). With this change, we should be
able to run 64 little endian elf binaries executing previleged
instructions with translation off.

Change-Id: Iaa64a37676874cee1ed1a0591b51b5e842774b45
Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by:  Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>

diff --git a/src/arch/power/isa.cc b/src/arch/power/isa.cc
index 87eb71674ccd683d89550b6a716b0d215bea0e2e..8d0942e9f2ca6e3565ef82f8670896e6ed127c3d 100644 (file)
--- a/src/arch/power/isa.cc
+++ b/src/arch/power/isa.cc
@@ -37,6 +37,8 @@
 
 #include "arch/power/isa.hh"
 
+#include "arch/power/miscregs.hh"
+#include "cpu/base.hh"
 #include "params/PowerISA.hh"
 
 namespace PowerISA
@@ -53,6 +55,20 @@ ISA::params() const
     return dynamic_cast<const Params *>(_params);
 }
 
+MiscReg
+ISA::readMiscRegNoEffect(int misc_reg) const
+{
+    assert(isValidMiscReg(misc_reg));
+    return regVal[misc_reg];
+}
+
+void
+ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+{
+    assert(isValidMiscReg(misc_reg));
+    regVal[misc_reg] = val;
+}
+
 }
 
 PowerISA::ISA *

diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index a0d4a4660113af65beaf4620253b4639d158cc18..d48f2b13978ceaef1ada027d6da6eac84ad0b75b 100644 (file)
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -31,6 +31,7 @@
 #define __ARCH_POWER_ISA_HH__
 
 #include "arch/generic/isa.hh"
+#include "arch/power/miscregs.hh"
 #include "arch/power/registers.hh"
 #include "arch/power/types.hh"
 #include "base/logging.hh"
@@ -48,22 +49,19 @@ namespace PowerISA
 class ISA : public BaseISA
 {
   protected:
-    RegVal dummy;
-    RegVal miscRegs[NumMiscRegs];
+    MiscReg regVal[NumMiscRegs];
+    MiscReg dummy;
 
   public:
     typedef PowerISAParams Params;
-
-    void clear() {}
-
-  public:
-    RegVal
-    readMiscRegNoEffect(int misc_reg) const
+    void
+    clear()
     {
-        fatal("Power does not currently have any misc regs defined\n");
-        return dummy;
+        memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
     }
 
+    MiscReg readMiscRegNoEffect(int misc_reg) const;
+
     RegVal
     readMiscReg(int misc_reg)
     {
@@ -71,11 +69,7 @@ class ISA : public BaseISA
         return dummy;
     }
 
-    void
-    setMiscRegNoEffect(int misc_reg, RegVal val)
-    {
-        fatal("Power does not currently have any misc regs defined\n");
-    }
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 
     void
     setMiscReg(int misc_reg, RegVal val)

diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc
index 2726ca341f6a0cb6c7d4afcae64b18db70bcb283..5162764ca6c1b0f1d8ccb22df3907de2d9f2d7dc 100644 (file)
--- a/src/arch/power/tlb.cc
+++ b/src/arch/power/tlb.cc
@@ -35,7 +35,9 @@
 #include <vector>
 
 #include "arch/power/faults.hh"
+#include "arch/power/miscregs.hh"
 #include "arch/power/pagetable.hh"
+#include "arch/power/registers.hh"
 #include "arch/power/utility.hh"
 #include "base/inifile.hh"
 #include "base/str.hh"
@@ -237,13 +239,39 @@ TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
 Fault
 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
 {
-    panic_if(FullSystem,
-            "translateAtomic not yet implemented for full system.");
-
+    if (FullSystem){
+       Msr msr = tc->readIntReg(MISCREG_MSR);
+        if (mode == Execute){
+            if (msr.ir)
+                fatal("Translate Atomic not Implemented for POWER");
+            else{
+                Addr vaddr = req->getVaddr();
+                DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
+                Addr paddr = vaddr;
+                DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
+                req->setPaddr(paddr);
+                return NoFault;
+            }
+        }
+        else{
+            if (msr.dr)
+                fatal("Translate Atomic not Implemented for POWER");
+            else{
+                Addr vaddr = req->getVaddr();
+                DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
+                Addr paddr = vaddr;
+                DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
+                req->setPaddr(paddr);
+                return NoFault;
+            }
+        }
+    }
     if (mode == Execute)
-        return translateInst(req, tc);
-    else
+         return translateInst(req, tc);
+    else{
+        std::cout<<"translateData"<<std::endl;
         return translateData(req, tc, mode == Write);
+   }
 }
 
 Fault