mips.h (SLOW_BYTE_ACCESS): Turn off for MIPS16.

2007-04-28  Sandra Loosemore  <sandra@codesourcery.com>
	    Nigel Stephens  <nigel@mips.com>

	gcc/
	* config/mips/mips.h (SLOW_BYTE_ACCESS): Turn off for MIPS16.

Co-Authored-By: Nigel Stephens <nigel@mips.com>
From-SVN: r124261

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 682195135c53ece36ddda2206e4a43935e6a2f88..c6282e0a9eb0d40cf3b97db7c4b492c9409ce1b9 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2007-04-28  Sandra Loosemore  <sandra@codesourcery.com>
+           Nigel Stephens  <nigel@mips.com>
+
+       * config/mips/mips.h (SLOW_BYTE_ACCESS): Turn off for MIPS16.
+
 2007-04-28  Jan Hubicka  <jh@suse.cz>
 
        * config/alpha/alpha.c (alpha_output_mi_thunk_osf): Use

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 72845436cfdfe92aa677681d18ca62531c7de290..e3c631e087e5f68b04df78b356b79df67cdf0cc7 100644 (file)
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -2240,8 +2240,11 @@ typedef struct mips_args {
    difference in cost between byte and (aligned) word loads.
 
    On RISC machines, it tends to generate better code to define
-   this as 1, since it avoids making a QI or HI mode register.  */
-#define SLOW_BYTE_ACCESS 1
+   this as 1, since it avoids making a QI or HI mode register.
+
+   But, generating word accesses for -mips16 is generally bad as shifts
+   (often extended) would be needed for byte accesses.  */
+#define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
 
 /* Define this to be nonzero if shift instructions ignore all but the low-order
    few bits.  */