struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
+ uint32_t index_max_size = 0;
+ uint64_t index_va = 0;
if (info->count_from_stream_output) {
struct r600_so_target *t =
assert(!"unreachable");
return;
}
+
+ index_max_size = (ib->buffer->width0 - ib->offset) /
+ ib->index_size;
+ index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
+
+ assert(index_va % 2 == 0);
+
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ (struct r600_resource *)ib->buffer,
+ RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
}
if (!info->indirect) {
}
if (info->indexed) {
- uint32_t index_max_size = (ib->buffer->width0 - ib->offset) /
- ib->index_size;
- uint64_t index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
-
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
- (struct r600_resource *)ib->buffer,
- RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
-
if (info->indirect) {
- assert(index_va % 2 == 0);
assert(info->indirect_offset % 4 == 0);
radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));