[libre-riscv-dev] NLNet018TV documentation

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+From: Staf Verhaegen <staf@fibraservi.eu>
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+Date: Fri, 05 Jun 2020 18:44:50 +0200
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+Subject: [libre-riscv-dev] NLNet018TV documentation
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+Goodday all,
+
+I did tape-out the TSMC 0.18=C2=B5m test chip around a week ago and am now
+hard at work in documenting was is on the chip. I just pushed first
+version of the documentation and can be found in the designs/NLNet018TV
+ directory on my SnowWhite repo on gitlab. Currently it only discusses
+what is on the design; not why these structures are there with this
+design. This is planned for later. Next step is to add a test plan and
+then blog about it.
+
+Most significant change is that I did not put a full SRAM block on the
+design but single SRAM cells only. This was both due the limited
+availability of IO pins and the time pressure of the tape-out deadline.
+Instead more focus was put on the design of the IO cells which is
+actually the main reason of this test chip.
+
+I did currently have three different drive strengths for the source and
+sink drivers next to the pull-up/pull-down functionality.
+The highest drive strength of 230mA is meant for driving resistive
+loads like for example LEDS. The real current will most of the time be
+limited by an external resistor in order to limit the heating of the
+chip. This is one the things that will be measured during testing.
+These test chips are wirebonded semi-manually and to ease it a pitch of
+90=C2=B5m between the IO cells is used. The 230mA driver strength is the
+result of filling up the total width of the IO cell with drivers.
+Depending on the number of outputs for the prototype we may negotiate a
+smaller pitch but this will also reduce the drive strength of this big
+driver or alternatively the IO cell may need to be made higher.
+The two lower drive strength are meant to drive capacitive loads. They
+can be either used alone or combined giving possibility of having 10mA,
+20mA or 30mA (e.g. 10mA + 20mA) drivers. It allows to configure them as
+having the driver sink or source current or both. Reason I choose these
+drive strengths is that the 10mA corresponds with one transistor needed
+to fulfill the ESD design rules and in simulation I did see acceptable
+output over/undershoot even with minimal capacitive load. From
+simulation a 40mA driver gave significant overshoot/undershoot and
+oscillation even with high capacitive loads.
+The design of the IO cell is quite flexible and can still be adapted if
+there would be special needs for the prototype. So I am interested to
+know what changes you think are needed for the prototype.
+
+greets,
+Staf.
+
+
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