mem: add request types for acquire and release

Add support for acquire and release requests.  These synchronization operations
are commonly supported by several modern instruction sets.

diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 7fe152f7da0dbe6d943d8a57ab324d79ab9ba4b7..bda5ff24fdf4ad56aa1cecd796dc164fbaf6693e 100644 (file)
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -12,7 +12,7 @@
  * modified or unmodified, in source code or in binary form.
  *
  * Copyright (c) 2006 The Regents of The University of Michigan
- * Copyright (c) 2010 Advanced Micro Devices, Inc.
+ * Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -165,6 +165,14 @@ MemCmd::commandInfo[] =
         MessageResp, "MessageReq" },
     /* IntResp -- for interrupts */
     { SET2(IsWrite, IsResponse), InvalidCmd, "MessageResp" },
+    /* ReleaseReq -- for release synchronization */
+    { SET3(IsRelease, IsRequest, NeedsResponse), ReleaseResp, "ReleaseReq" },
+    /* ReleaseResp -- for release synchronization */
+    { SET2(IsRelease, IsResponse), InvalidCmd, "ReleaseResp" },
+    /* AcquireReq -- for release synchronization */
+    { SET3(IsAcquire, IsRequest, NeedsResponse), AcquireResp, "AcquireReq" },
+    /* AcquireResp -- for release synchronization */
+    { SET3(IsAcquire, IsResponse, NeedsResponse), InvalidCmd, "AcquireResp" },
     /* InvalidDestError  -- packet dest field invalid */
     { SET2(IsResponse, IsError), InvalidCmd, "InvalidDestError" },
     /* BadAddressError   -- memory address invalid */

diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index d1774e5a8126ee74d860d91d2fb8510dda2465b8..1cbe6e499e570a70ffc9d753cf7a0078cd32207f 100644 (file)
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -12,7 +12,7 @@
  * modified or unmodified, in source code or in binary form.
  *
  * Copyright (c) 2006 The Regents of The University of Michigan
- * Copyright (c) 2010 Advanced Micro Devices, Inc.
+ * Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -110,6 +110,10 @@ class MemCmd
         SwapResp,
         MessageReq,
         MessageResp,
+        ReleaseReq,
+        ReleaseResp,
+        AcquireReq,
+        AcquireResp,
         // Error responses
         // @TODO these should be classified as responses rather than
         // requests; coding them as requests initially for backwards
@@ -147,6 +151,8 @@ class MemCmd
         IsError,        //!< Error response
         IsPrint,        //!< Print state matching address (for debugging)
         IsFlush,        //!< Flush the address from caches
+        IsAcquire,      //!< Acquire operation
+        IsRelease,      //!< Release operation
         NUM_COMMAND_ATTRIBUTES
     };
 
@@ -203,6 +209,8 @@ class MemCmd
     bool isError() const        { return testCmdAttrib(IsError); }
     bool isPrint() const        { return testCmdAttrib(IsPrint); }
     bool isFlush() const        { return testCmdAttrib(IsFlush); }
+    bool isAcquire() const      { return testCmdAttrib(IsAcquire); }
+    bool isRelease() const      { return testCmdAttrib(IsRelease); }
 
     const Command
     responseCommand() const
@@ -484,6 +492,8 @@ class Packet : public Printable
     bool isError() const             { return cmd.isError(); }
     bool isPrint() const             { return cmd.isPrint(); }
     bool isFlush() const             { return cmd.isFlush(); }
+    bool isAcquire() const           { return cmd.isAcquire(); }
+    bool isRelease() const           { return cmd.isRelease(); }
 
     // Snoop flags
     void assertMemInhibit()

diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
index 20ef697c548f7be7446f533d752cd521f88eddf8..1d591482de8c402b11659aedee82b0cc03f5200c 100644 (file)
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -136,6 +136,9 @@ enumeration(RubyRequestType, desc="...", default="RubyRequestType_NULL") {
   COMMIT,            desc="Commit version";
   NULL,              desc="Invalid request type";
   FLUSH,             desc="Flush request type";
+  Release,           desc="Release operation";
+  Acquire,           desc="Acquire opertion";
+  AcquireRelease,    desc="Acquire and Release opertion";
 }
 
 enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") {

diff --git a/src/mem/request.hh b/src/mem/request.hh
index cf8d27939ec20e3bc02f8abfab4d30f9e421f857..ae66042222dbf082b40e9576d6de6bdabfcb29d2 100644 (file)
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -12,6 +12,7 @@
  * modified or unmodified, in source code or in binary form.
  *
  * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -85,7 +86,7 @@ typedef uint16_t MasterID;
 class Request
 {
   public:
-    typedef uint32_t FlagsType;
+    typedef uint64_t FlagsType;
     typedef uint8_t ArchFlagsType;
     typedef ::Flags<FlagsType> Flags;
 
@@ -97,11 +98,11 @@ class Request
          * architecture-specific code. For example, SPARC uses them to
          * represent ASIs.
          */
-        ARCH_BITS                   = 0x000000FF,
+        ARCH_BITS                   = 0x00000000000000FF,
         /** The request was an instruction fetch. */
-        INST_FETCH                  = 0x00000100,
+        INST_FETCH                  = 0x0000000000000100,
         /** The virtual address is also the physical address. */
-        PHYSICAL                    = 0x00000200,
+        PHYSICAL                    = 0x0000000000000200,
         /**
          * The request is to an uncacheable address.
          *
@@ -109,7 +110,7 @@ class Request
          * STRICT_ORDER flag should be set if such reordering is
          * undesirable.
          */
-        UNCACHEABLE                = 0x00000400,
+        UNCACHEABLE                = 0x0000000000000400,
         /**
          * The request is required to be strictly ordered by <i>CPU
          * models</i> and is non-speculative.
@@ -119,22 +120,22 @@ class Request
          * memory system may still reorder requests in caches unless
          * the UNCACHEABLE flag is set as well.
          */
-        STRICT_ORDER                = 0x00000800,
+        STRICT_ORDER                = 0x0000000000000800,
         /** This request is to a memory mapped register. */
-        MMAPPED_IPR                 = 0x00002000,
+        MMAPPED_IPR                 = 0x0000000000001000,
         /** This request is a clear exclusive. */
-        CLEAR_LL                    = 0x00004000,
+        CLEAR_LL                    = 0x0000000000002000,
         /** This request is made in privileged mode. */
-        PRIVILEGED                  = 0x00008000,
+        PRIVILEGED                  = 0x0000000000004000,
 
         /**
          * This is a write that is targeted and zeroing an entire
          * cache block.  There is no need for a read/modify/write
          */
-        CACHE_BLOCK_ZERO            = 0x00010000,
+        CACHE_BLOCK_ZERO            = 0x0000000000008000,
 
         /** The request should not cause a memory access. */
-        NO_ACCESS                   = 0x00080000,
+        NO_ACCESS                   = 0x0000000000100000,
         /**
          * This request will lock or unlock the accessed memory. When
          * used with a load, the access locks the particular chunk of
@@ -142,30 +143,34 @@ class Request
          * that locked accesses have to be made up of a locked load,
          * some operation on the data, and then a locked store.
          */
-        LOCKED_RMW                  = 0x00100000,
+        LOCKED_RMW                  = 0x0000000000200000,
         /** The request is a Load locked/store conditional. */
-        LLSC                        = 0x00200000,
+        LLSC                        = 0x0000000000400000,
         /** This request is for a memory swap. */
-        MEM_SWAP                    = 0x00400000,
-        MEM_SWAP_COND               = 0x00800000,
+        MEM_SWAP                    = 0x0000000000800000,
+        MEM_SWAP_COND               = 0x0000000001000000,
 
         /** The request is a prefetch. */
-        PREFETCH                    = 0x01000000,
+        PREFETCH                    = 0x0000000002000000,
         /** The request should be prefetched into the exclusive state. */
-        PF_EXCLUSIVE                = 0x02000000,
+        PF_EXCLUSIVE                = 0x0000000004000000,
         /** The request should be marked as LRU. */
-        EVICT_NEXT                  = 0x04000000,
+        EVICT_NEXT                  = 0x0000000008000000,
+        /** The request should be marked with ACQUIRE. */
+        ACQUIRE                     = 0x0000000001000000,
+        /** The request should be marked with RELEASE. */
+        RELEASE                     = 0x0000000002000000,
 
         /**
          * The request should be handled by the generic IPR code (only
          * valid together with MMAPPED_IPR)
          */
-        GENERIC_IPR                 = 0x08000000,
+        GENERIC_IPR                 = 0x0000000004000000,
 
         /** The request targets the secure memory space. */
-        SECURE                      = 0x10000000,
+        SECURE                      = 0x0000000008000000,
         /** The request is a page table walk */
-        PT_WALK                     = 0x20000000,
+        PT_WALK                     = 0x0000000010000000,
 
         /**
          * These flags are *not* cleared when a Request object is
@@ -655,12 +660,19 @@ class Request
     bool isLLSC() const { return _flags.isSet(LLSC); }
     bool isPriv() const { return _flags.isSet(PRIVILEGED); }
     bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
+    bool isAcquire() const { return _flags.isSet(ACQUIRE); }
+    bool isRelease() const { return _flags.isSet(RELEASE); }
+    bool isAcquireRelease() const {
+        return _flags.isSet(RELEASE | ACQUIRE);
+    }
     bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
     bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
     bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
     bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
     bool isSecure() const { return _flags.isSet(SECURE); }
     bool isPTWalk() const { return _flags.isSet(PT_WALK); }
+    void setAcquire() { _flags.set(ACQUIRE); }
+    void setRelease() { _flags.set(RELEASE); }
 };
 
 #endif // __MEM_REQUEST_HH__