config: Fix the cache class naming in regression scripts

This patch unifies the naming of the default L1 and L2 caches in the
regression configs to be in line with what is used in the se and fs
scripts.

diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 867d0cb2e2e6076f78b7d097e7ee21f60de6d17a..e6cbb1a75b3cdced06171dfd5bbc8b55697f1e45 100644 (file)
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -46,7 +46,7 @@ from m5.objects import *
 # starting point, and specific parameters can be overridden in the
 # specific instantiations.
 
-class L1(BaseCache):
+class L1Cache(BaseCache):
     assoc = 2
     hit_latency = 2
     response_latency = 2
@@ -55,7 +55,7 @@ class L1(BaseCache):
     tgts_per_mshr = 20
     is_top_level = True
 
-class L2(BaseCache):
+class L2Cache(BaseCache):
     assoc = 8
     block_size = 64
     hit_latency = 20
@@ -84,4 +84,3 @@ class PageTableWalkerCache(BaseCache):
     size = '1kB'
     tgts_per_mshr = 12
     is_top_level = True
-

diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 2b611fb9d3f19afcc5c97fd372348c485d83d0b9..6f3bddc6f09ffe848291c3164c47f4a716a2f169 100644 (file)
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -39,7 +39,7 @@ system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus())
 
 # l2cache & bus
 system.toL2Bus = CoherentBus(clock = '2GHz')
-system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 
 # connect l2c to membus
@@ -47,8 +47,8 @@ system.l2c.mem_side = system.membus.slave
 
 # add L1 caches
 for cpu in cpus:
-    cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                                L1(size = '32kB', assoc = 4))
+    cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
+                                L1Cache(size = '32kB', assoc = 4))
     # create the interrupt controller
     cpu.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache

diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py
index c4317ec23efd3e95dc322278191809097b54884b..6bab4c448ff1441fa47268682c5221a0f2edee54 100644 (file)
--- a/tests/configs/pc-o3-timing.py
+++ b/tests/configs/pc-o3-timing.py
@@ -50,9 +50,9 @@ system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 #connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
-                              L1(size = '32kB', assoc = 4),
-                              L2(size = '4MB', assoc = 8),
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4),
+                              L2Cache(size = '4MB', assoc = 8),
                               PageTableWalkerCache(),
                               PageTableWalkerCache())
 # create the interrupt controller

diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py
index 44ba51b3c1b11c1ecc2b9a8a19fd976ea8651565..74d47fe417d41883e7b0ab37c8273969b6c42b28 100644 (file)
--- a/tests/configs/pc-simple-atomic.py
+++ b/tests/configs/pc-simple-atomic.py
@@ -50,9 +50,9 @@ system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 #connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
-                              L1(size = '32kB', assoc = 4),
-                              L2(size = '4MB', assoc = 8),
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4),
+                              L2Cache(size = '4MB', assoc = 8),
                               PageTableWalkerCache(),
                               PageTableWalkerCache())
 # create the interrupt controller

diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py
index 99017900839f5cd6f8e657fa17744b6e91549eec..1b7e809f71a2183f8ad976d64893bbb89adc97d0 100644 (file)
--- a/tests/configs/pc-simple-timing.py
+++ b/tests/configs/pc-simple-timing.py
@@ -50,9 +50,9 @@ system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 #connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
-                              L1(size = '32kB', assoc = 4),
-                              L2(size = '4MB', assoc = 8),
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4),
+                              L2Cache(size = '4MB', assoc = 8),
                               PageTableWalkerCache(),
                               PageTableWalkerCache())
 # create the interrupt controller

diff --git a/tests/configs/realview-o3-checker.py b/tests/configs/realview-o3-checker.py
index 248a1d41b2ca80918d45033f5278af6fe75f6dfd..8c5d4086dadb5724a851832184c09b9219dc7d4a 100644 (file)
--- a/tests/configs/realview-o3-checker.py
+++ b/tests/configs/realview-o3-checker.py
@@ -56,9 +56,9 @@ system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 #connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
-                              L1(size = '32kB', assoc = 4),
-                              L2(size = '4MB', assoc = 8))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4),
+                              L2Cache(size = '4MB', assoc = 8))
 # create the interrupt controller
 cpu.createInterruptController()
 # connect cpu and caches to the rest of the system

diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py
index cc4fa236fb48adf031be5f93fdcaa3ac7c9411ea..b5c235a67560e99ab18786eeced70de5036bd1a2 100644 (file)
--- a/tests/configs/realview-o3-dual.py
+++ b/tests/configs/realview-o3-dual.py
@@ -46,14 +46,14 @@ system.cpu = cpus
 system.toL2Bus = CoherentBus(clock = '2GHz')
 
 #connect up the l2 cache
-system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 system.l2c.mem_side = system.membus.slave
 
 #connect up the cpu and l1s
 for c in cpus:
-    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                                L1(size = '32kB', assoc = 4))
+    c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4))
     # create the interrupt controller
     c.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache

diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py
index 6f98309fe812f0f0a21c133d727e5210365b20d2..6dbc0c828bff7a3d7265e0c3db64fcfbbf7ea12d 100644 (file)
--- a/tests/configs/realview-o3.py
+++ b/tests/configs/realview-o3.py
@@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 #connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
-                              L1(size = '32kB', assoc = 4),
-                              L2(size = '4MB', assoc = 8))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4),
+                              L2Cache(size = '4MB', assoc = 8))
 # create the interrupt controller
 cpu.createInterruptController()
 # connect cpu and caches to the rest of the system

diff --git a/tests/configs/realview-simple-atomic-dual.py b/tests/configs/realview-simple-atomic-dual.py
index b26272a9104f05fed34107ccda4720eb29ac5b1e..90a9d5537992ee88a74d5af2c824eeda78e16929 100644 (file)
--- a/tests/configs/realview-simple-atomic-dual.py
+++ b/tests/configs/realview-simple-atomic-dual.py
@@ -46,14 +46,14 @@ system.cpu = cpus
 system.toL2Bus = CoherentBus(clock = '2GHz')
 
 #connect up the l2 cache
-system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 system.l2c.mem_side = system.membus.slave
 
 #connect up the cpu and l1s
 for c in cpus:
-    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                                L1(size = '32kB', assoc = 4))
+    c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4))
     # create the interrupt controller
     c.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache

diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py
index 2d1efe3fe871dfb18c141939e985ada56da0224d..5cad3a2cbfd4cb14dce06ce70cd8c8b8d96c71b5 100644 (file)
--- a/tests/configs/realview-simple-atomic.py
+++ b/tests/configs/realview-simple-atomic.py
@@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 #connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
-                              L1(size = '32kB', assoc = 4),
-                              L2(size = '4MB', assoc = 8))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4),
+                              L2Cache(size = '4MB', assoc = 8))
 # create the interrupt controller
 cpu.createInterruptController()
 # connect cpu and caches to the rest of the system

diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py
index 1c86f42bfc7b01511fb70f83f945eb556e2ca37f..5b8e6e0e3da503ae9571a2d6d67b9f6e341c8d5e 100644 (file)
--- a/tests/configs/realview-simple-timing-dual.py
+++ b/tests/configs/realview-simple-timing-dual.py
@@ -46,14 +46,14 @@ system.cpu = cpus
 system.toL2Bus = CoherentBus(clock = '2GHz')
 
 #connect up the l2 cache
-system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 system.l2c.mem_side = system.membus.slave
 
 #connect up the cpu and l1s
 for c in cpus:
-    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                                L1(size = '32kB', assoc = 4))
+    c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4))
     # create the interrupt controller
     c.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache

diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index 4bb641e808481478c56698e6b5d7972d8afe41a4..c2dc27b48698c5e9c4c7bc534b6b22ce3aebf5b3 100644 (file)
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 #connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
-                              L1(size = '32kB', assoc = 4),
-                              L2(size = '4MB', assoc = 8))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4),
+                              L2Cache(size = '4MB', assoc = 8))
 # create the interrupt controller
 cpu.createInterruptController()
 # connect cpu and caches to the rest of the system

diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py
index 0d7e817e0f810b427ed2c319aec44b77d3b7651c..b0aa1c7cdae2fdd124ceab79ad1d22092e6f244d 100644 (file)
--- a/tests/configs/tsunami-inorder.py
+++ b/tests/configs/tsunami-inorder.py
@@ -48,9 +48,9 @@ system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 #connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
-                              L1(size = '32kB', assoc = 4),
-                              L2(size = '4MB', assoc = 8))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4),
+                              L2Cache(size = '4MB', assoc = 8))
 # create the interrupt controller
 cpu.createInterruptController()
 # connect cpu and caches to the rest of the system

diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index a1564f8f8d3353b065788bf715684f3329313473..9aac5e744c2dd6416e526fcb51a55f577d0873c5 100644 (file)
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -46,14 +46,14 @@ system.iocache.mem_side = system.membus.slave
 
 
 #connect up the l2 cache
-system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 system.l2c.mem_side = system.membus.slave
 
 #connect up the cpu and l1s
 for c in cpus:
-    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                                L1(size = '32kB', assoc = 4))
+    c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4))
     # create the interrupt controller
     c.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache

diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index 18cbf1db1dd59c2b32dedbcef0627db04d552183..d50b59257949afd233867f70964972007f01c42a 100644 (file)
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 #connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
-                              L1(size = '32kB', assoc = 4),
-                              L2(size = '4MB', assoc = 8))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4),
+                              L2Cache(size = '4MB', assoc = 8))
 # create the interrupt controller
 cpu.createInterruptController()
 # connect cpu and caches to the rest of the system

diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 1f63ff7a84b43b35a0410abf08b14b4c030ae5fa..b91d56cec3078a1ab335c0b715a7a1acc2a27b22 100644 (file)
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -45,14 +45,14 @@ system.cpu = cpus
 system.toL2Bus = CoherentBus(clock = '2GHz')
 
 #connect up the l2 cache
-system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 system.l2c.mem_side = system.membus.slave
 
 #connect up the cpu and l1s
 for c in cpus:
-    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                                L1(size = '32kB', assoc = 4))
+    c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4))
     # create the interrupt controller
     c.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache

diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index 9c7e5c265d4a909e1aa418c4ee0c1b7eee5872be..bbab929cdf6dc3534314af426149faa5df6a8238 100644 (file)
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 #connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
-                              L1(size = '32kB', assoc = 4),
-                              L2(size = '4MB', assoc = 8))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4),
+                              L2Cache(size = '4MB', assoc = 8))
 # create the interrupt controller
 cpu.createInterruptController()
 # connect cpu and caches to the rest of the system

diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index 8bac5bd903abf154090d6ba4524ce21819da0c7f..4d74d905753dc1522b1c6ca7e4ab3a7dde0d97c0 100644 (file)
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -45,14 +45,14 @@ system.cpu = cpus
 system.toL2Bus = CoherentBus(clock = '2GHz')
 
 #connect up the l2 cache
-system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 system.l2c.mem_side = system.membus.slave
 
 #connect up the cpu and l1s
 for c in cpus:
-    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                                L1(size = '32kB', assoc = 4))
+    c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4))
     # create the interrupt controller
     c.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache

diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 60b4e47f475686d4fc4325b36be0663284106b33..7bba6f938ac5d1dcbd8a73224055abed2136b154 100644 (file)
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
 #connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
-                              L1(size = '32kB', assoc = 4),
-                              L2(size = '4MB', assoc = 8))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+                              L1Cache(size = '32kB', assoc = 4),
+                              L2Cache(size = '4MB', assoc = 8))
 # create the interrupt controller
 cpu.createInterruptController()
 # connect cpu and caches to the rest of the system