More {Itb,Dtb} -> {ITB,DTB} renames (forgot to test build KERNEL).
authorSteve Reinhardt <stever@eecs.umich.edu>
Sat, 3 Apr 2004 21:46:10 +0000 (13:46 -0800)
committerSteve Reinhardt <stever@eecs.umich.edu>
Sat, 3 Apr 2004 21:46:10 +0000 (13:46 -0800)
Also missed renames in a bunch of config files somehow.
(See previous changeset for list of renames.)

arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/faults.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
    More {Itb,Dtb} -> {ITB,DTB} renames (forgot to test build KERNEL).

--HG--
extra : convert_revision : b2c6ca0916b72b59895520fcacaf028667560a0d

arch/alpha/alpha_memory.cc
arch/alpha/ev5.cc
arch/alpha/faults.hh
cpu/exec_context.cc
cpu/exec_context.hh
cpu/simple_cpu/simple_cpu.hh

index 13cdb1d732b717766645e67a793fdc91755afc23..dea25a44071d64d89c71050f906379ac04c13c13 100644 (file)
@@ -465,7 +465,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
                   req->xc);
 
             if (write) { write_acv++; } else { read_acv++; }
-            return Dtb_Fault_Fault;
+            return DTB_Fault_Fault;
         }
 
         // Check for "superpage" mapping: when SP<1> is set, and
@@ -480,7 +480,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
                       ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_ACV_MASK),
                       req->xc);
                 if (write) { write_acv++; } else { read_acv++; }
-                return Dtb_Acv_Fault;
+                return DTB_Acv_Fault;
             }
 
             req->paddr = req->vaddr & PA_IMPL_MASK;
@@ -512,13 +512,13 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
                           (pte->fonw ? MM_STAT_FONW_MASK : 0),
                           req->xc);
                     write_acv++;
-                    return Dtb_Fault_Fault;
+                    return DTB_Fault_Fault;
                 }
                 if (pte->fonw) {
                     fault(req->vaddr, MM_STAT_WR_MASK | MM_STAT_FONW_MASK,
                           req->xc);
                     write_acv++;
-                    return Dtb_Fault_Fault;
+                    return DTB_Fault_Fault;
                 }
             } else {
                 if (!(pte->xre & MODE2MASK(mode))) {
@@ -527,12 +527,12 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
                           (pte->fonr ? MM_STAT_FONR_MASK : 0),
                           req->xc);
                     read_acv++;
-                    return Dtb_Acv_Fault;
+                    return DTB_Acv_Fault;
                 }
                 if (pte->fonr) {
                     fault(req->vaddr, MM_STAT_FONR_MASK, req->xc);
                     read_acv++;
-                    return Dtb_Fault_Fault;
+                    return DTB_Fault_Fault;
                 }
             }
         }
index 551cbdabfda7737430ff1a830edf619da395ee00..9b3ac5fff7cfc7d6121c66412fc96ffe624ce1e9 100644 (file)
@@ -68,11 +68,11 @@ AlphaISA::fault_addr[Num_Faults] = {
     0x0201,    /* Ndtb_Miss_Fault */
     0x0281,    /* Pdtb_Miss_Fault */
     0x0301,    /* Alignment_Fault */
-    0x0381,    /* Dtb_Fault_Fault */
-    0x0381,    /* Dtb_Acv_Fault */
-    0x0181,    /* Itb_Miss_Fault */
-    0x0181,    /* Itb_Fault_Fault */
-    0x0081,    /* Itb_Acv_Fault */
+    0x0381,    /* DTB_Fault_Fault */
+    0x0381,    /* DTB_Acv_Fault */
+    0x0181,    /* ITB_Miss_Fault */
+    0x0181,    /* ITB_Fault_Fault */
+    0x0081,    /* ITB_Acv_Fault */
     0x0481,    /* Unimplemented_Opcode_Fault */
     0x0581,    /* Fen_Fault */
     0x2001,    /* Pal_Fault */
index bc8a4da0ed7708a130671d4607f93bdb26b75416..33aa5543965e535af44c3037860a8e251181d9cc 100644 (file)
@@ -38,11 +38,11 @@ enum Fault {
     Ndtb_Miss_Fault,           // DTB miss
     Pdtb_Miss_Fault,           // nested DTB miss
     Alignment_Fault,           // unaligned access
-    Dtb_Fault_Fault,           // DTB page fault
-    Dtb_Acv_Fault,             // DTB access violation
-    Itb_Miss_Fault,            // ITB miss
-    Itb_Fault_Fault,           // ITB page fault
-    Itb_Acv_Fault,             // ITB access violation
+    DTB_Fault_Fault,           // DTB page fault
+    DTB_Acv_Fault,             // DTB access violation
+    ITB_Miss_Fault,            // ITB miss
+    ITB_Fault_Fault,           // ITB page fault
+    ITB_Acv_Fault,             // ITB access violation
     Unimplemented_Opcode_Fault,        // invalid/unimplemented instruction
     Fen_Fault,                 // FP not-enabled fault
     Pal_Fault,                 // call_pal S/W interrupt
index e7d3e0b91a9a77cfc8b2a51641ddc627d9b3d68b..a89cf4bb522bba586ddac6b50f0d2ae6ae764a54 100644 (file)
@@ -42,7 +42,7 @@ using namespace std;
 // constructor
 #ifdef FULL_SYSTEM
 ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
-                         AlphaItb *_itb, AlphaDtb *_dtb,
+                         AlphaITB *_itb, AlphaDTB *_dtb,
                          FunctionalMemory *_mem)
     : _status(ExecContext::Unallocated),
       kernelStats(this, _cpu), cpu(_cpu), thread_num(_thread_num),
index a72516ac7cfb9254a32888ac4f3a304670695360..f2f2c0879059a3d187e6522c4f6aa296277bd2ab 100644 (file)
@@ -124,8 +124,8 @@ class ExecContext
 #ifdef FULL_SYSTEM
 
     FunctionalMemory *mem;
-    AlphaItb *itb;
-    AlphaDtb *dtb;
+    AlphaITB *itb;
+    AlphaDTB *dtb;
     System *system;
 
     // the following two fields are redundant, since we can always
@@ -174,7 +174,7 @@ class ExecContext
     // constructor: initialize context from given process structure
 #ifdef FULL_SYSTEM
     ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
-                AlphaItb *_itb, AlphaDtb *_dtb, FunctionalMemory *_dem);
+                AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
 #else
     ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
     ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
index 9edd66ab41cec0b8ceabbc524a33a9c9031119f0..d634753b95ddac4c6ec7d0d59d25bb11fbd14deb 100644 (file)
@@ -40,8 +40,8 @@
 #ifdef FULL_SYSTEM
 class Processor;
 class Kernel;
-class AlphaItb;
-class AlphaDtb;
+class AlphaITB;
+class AlphaDTB;
 class PhysicalMemory;
 
 class RemoteGDB;
@@ -131,7 +131,7 @@ class SimpleCPU : public BaseCPU
               System *_system,
               Counter max_insts_any_thread, Counter max_insts_all_threads,
               Counter max_loads_any_thread, Counter max_loads_all_threads,
-              AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem,
+              AlphaITB *itb, AlphaDTB *dtb, FunctionalMemory *mem,
               MemInterface *icache_interface, MemInterface *dcache_interface,
               bool _def_reg, Tick freq);