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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 1552a12a8386c2d5e33432482f9dc50ce1cb91b8..4b843a0f50373e4cad25ab622dce6880871bebbb 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -17,7 +17,27 @@ multiple billion-dollar-revenue companies, to sustain them.
 Therefore it begs the question, why on earth would anyone consider this
 task?
 
-Hints as to the answer emerge from an article
+First hints are that whilst memory bitcells have not increased in
+speed since the 90s (around 150 mhz), increasing the datapath widths
+has allowed significant apparent speed increases: 3200 mhz DDR4 and
+even faster DDR5, and other advanced Memory interfaces such as HBM,
+Gen-Z, and OpenCAPI, all make an effort, but these efforts are
+dwarfed by the two nearly three orders of magnitude increase in
+CPU horsepower.  Some systems at the time of writing are approaching
+a *Gigabyte* of L4 Cache, by way of compensation.
+
+Efforts to solve this problem by moving the processing closer to
+or directly integrated into the memory have traditionally not gone
+well: Aspex Microelectronics, Elixent, these are parallel processing
+companies that very few have heard of, because their software stack
+was so specialist that it required heavy investment by customers to
+utilise.  D-Matrix and Graphcore are a modern incarnation of the exact
+same "specialist parallel processing" mistake, betting heavily on
+AI with Matrix and Convolution Engines that can do no other task.
+Aspex only survived by being bought by Ericsson, where its specialised
+suitability for massive wide Baseband FFTs saved it from going under.
+
+Second hints as to the answer emerge from an article
 "[SIMD considered harmful](https://www.sigarch.org/simd-instructions-considered-harmful/)"
 which illustrates a catastrophic rabbit-hole taken by Industry Giants
 ARM, Intel, AMD,