(no commit message)

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index 0ac865971ffa7107ca19662f63195582366f6adc..955955a6b4693d9b2c1d86b3b0cee3fac68dd7d0 100644 (file)
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -115,9 +115,9 @@ mantissa may be achieved.
 
 *IBM may consider it worthwhile to extend these two instructions to
 v3.1 Prefixed (`pfmvis` and `pfrlsi`). If so it is recommended that
-`pfmvis` load a full FP32 immediate and `pfrlsi` supplies the four high
-missing exponent bits (8 to 10) and the lower additional
-28 mantissa bits (23 to 51) needed to construct a full FP64 immediate.*
+`pfmvis` load a full FP32 immediate and `pfrlsi` supplies the three high
+missing exponent bits (numbered 8 to 10) and the lower additional
+29 mantissa bits (23 to 51) needed to construct a full FP64 immediate.*
 
 ## Load BF16 Immediate
 
@@ -179,14 +179,16 @@ DX-Form:
 Strategically similar to how `oris` is used to construct
 32-bit Integers, an additional 16-bits of immediate is
 inserted into `FRS` to extend its accuracy to
-a full FP32. If a prior `fmvis` instruction had been used to
+a full FP32 (stored as usual in FP64 Format within the FPR).
+If a prior `fmvis` instruction had been used to
 set the upper 16-bits of an FP32 value, `frlsi` contains the
 lower 16-bits.
 
 The key difference between using `li` and `oris` to construct 32-bit
 GPR Immediates and `frlsi` is that the `fmvis` will have converted
-the `BF16` to FP64 (Double) format. This is taken into consideration
-as can be seen in the pseudocode below
+the `BF16` immediate to FP64 (Double) format.
+This is taken into consideration
+as can be seen in the pseudocode below.
 
 Pseudocode: