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diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index b51923fa76e9e3e2b2f0b95f3010157503ad7899..6ce5edb3f7ec5add15afdc03338f5bcafb4850a8 100644 (file)
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -31,7 +31,7 @@ At its heart, SimpleV really is this simple.  On top of this fundamental basis f
 
 RISC-V RVV as of version 0.9 is over 180 instructions (more than the rest of RV64G combined). Over 95% of that functionality is added to OpenPOWER v3 0B, by SimpleV augmentation, with around 5 to 8 instructions.
 
-Even in OpenPOWER v3.0B, the Scalar Integer ISA is around 150 instructions, with IEEE754 FP adding approximately 80 more. VSX, being based on SIMD design principles, adds somewhere in the region of 600 more.
+Even in OpenPOWER v3.0B, the Scalar Integer ISA is around 150 instructions, with IEEE754 FP adding approximately 80 more. VSX, being based on SIMD design principles, adds somewhere in the region of 600 more.  SimpleV again provides over 95% of VSX functionality, simply by augmenting the *Scalar* OpenPOWER ISA, and in the process providing features such as predication, which VSX is entirely missing.
 
 The rest of this document builds on the above simple loop to add:
 
@@ -44,6 +44,18 @@ The rest of this document builds on the above simple loop to add:
 
 All of this is *without modifying the OpenPOWER v3.0B ISA*, except to add "wrapping context", similar to how v3.1B 64 Prefixes work.
 
+In fairness to both VSX and RVV, there are things that are not provided by SimpleV:
+
+* 128 bit or above arithmetic and other operations
+  (VSX Rijndael and SHA primitives; VSX shuffle operations)
+* register files above 128
+* Vector lengths over 64
+* Unit-strided LD/ST and other comprehensive memory operations
+  (struct-based LD/ST from RVV for example)
+* 32-bit instruction lengths. [[svp64]] had to be added as 64 bit.
+
+These are not insurmountable limitations, that, over time, may well be added in future revisions of SV. 
+