abc9_ops/write_xaiger: update doc

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 2d908e33b58c3d14c9cc721d564fbad44611c4a7..f9890a59210ae495d56801d6babc12a8e578310c 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -740,7 +740,8 @@ struct XAigerBackend : public Backend {
                log("Write the top module (according to the (* top *) attribute or if only one module\n");
                log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
                log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
-               log("pseudo-outputs.\n");
+               log("pseudo-outputs. Whitebox contents will be taken from the '<module-name>$holes'\n");
+               log("module, if it exists.\n");
                log("\n");
                log("    -ascii\n");
                log("        write ASCII version of AIGER format\n");

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 405f3e26726e5e947e1af44fab6658204f5b0949..463941b0b1b2dc9e54aa98c2bc07fbf91455ae00 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -739,6 +739,19 @@ struct Abc9OpsPass : public Pass {
                log("        '<module-name>$holes' module that contains the logic behaviour of ABC9\n");
                log("        whiteboxes.\n");
                log("\n");
+               log("    -dff\n");
+               log("        consider flop cells (those instantiating modules marked with (* abc9_flop *)\n");
+               log("        during -prep_xaiger.\n");
+               log("\n");
+               log("    -prep_dff\n");
+               log("        compute the clock domain and initial value of each flop in the design.\n");
+               log("        process the '$holes' module to support clock-enable functionality.\n");
+               log("\n");
+               log("    -reintegrate\n");
+               log("        for each selected module, re-intergrate the module '<module-name>$abc9'\n");
+               log("        by first recovering ABC9 boxes, and then stitching in the remaining primary\n");
+               log("        inputs and outputs.\n");
+               log("\n");
        }
        void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
        {