RISC-V: Add actual 'Zvkt' extension support
authorTsukasa OI <research_trasio@irq.a4lg.com>
Wed, 26 Jul 2023 01:39:44 +0000 (01:39 +0000)
committerTsukasa OI <research_trasio@irq.a4lg.com>
Fri, 28 Jul 2023 03:39:15 +0000 (03:39 +0000)
The 'Zvkt' extension is listed on the added extensions in the GNU Binutils
version 2.41 (see binutils/NEWS).  However, the support of this extension
was actually missing.

This commit adds actual support of this extension and adds implications
from 'Zvkn' and 'Zvks' superset extensions.

bfd/ChangeLog:

* elfxx-riscv.c (riscv_implicit_subsets) Add implications from
'Zvkn' and 'Zvks'.  (riscv_supported_std_z_ext): Add 'Zvkt' to
the supported extension list.

bfd/elfxx-riscv.c

index b43d2cfa0fab6876f46b33e6f75c99ad9130620a..ba5165766b2b149bd82e065fec64d870ddc7a695 100644 (file)
@@ -1162,6 +1162,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvkn", "zvknha",   check_implicit_always},
   {"zvkn", "zvknhb",   check_implicit_always},
   {"zvkn", "zvbb",     check_implicit_always},
+  {"zvkn", "zvkt",     check_implicit_always},
   {"zvkng", "zvkn",    check_implicit_always},
   {"zvkng", "zvkg",    check_implicit_always},
   {"zvknc", "zvkn",    check_implicit_always},
@@ -1169,6 +1170,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvks", "zvksed",   check_implicit_always},
   {"zvks", "zvksh",    check_implicit_always},
   {"zvks", "zvbb",     check_implicit_always},
+  {"zvks", "zvkt",     check_implicit_always},
   {"zvksg", "zvks",    check_implicit_always},
   {"zvksg", "zvkg",    check_implicit_always},
   {"zvksc", "zvks",    check_implicit_always},
@@ -1296,6 +1298,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvks",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvksg",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvksc",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
+  {"zvkt",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvl32b",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvl64b",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvl128b",          ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },