Fix when -dff not given

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 7ef744d04d050b6d5321a3cc042b8f493468ef10..32b218a22fb8d4194a76047cbf76ea7b40f679a6 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -239,17 +239,13 @@ struct XAigerWriter
 
                        RTLIL::Module* inst_module = module->design->module(cell->type);
                        if (inst_module) {
-                               bool abc9_box = inst_module->attributes.count("\\abc9_box_id");
-                               bool abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
-                               if (abc9_box && cell->get_bool_attribute("\\abc9_keep"))
-                                       abc9_box = false;
-
-                               if (abc9_box) {
-                                       int abc9_box_order = cell->attributes.at("\\abc9_box_order").as_int();
-                                       if (GetSize(box_list) <= abc9_box_order)
-                                               box_list.resize(abc9_box_order+1);
-                                       box_list[abc9_box_order] = cell;
-                                       if (!abc9_flop)
+                               auto it = cell->attributes.find("\\abc9_box_seq");
+                               if (it != cell->attributes.end()) {
+                                       int abc9_box_seq = it->second.as_int();
+                                       if (GetSize(box_list) <= abc9_box_seq)
+                                               box_list.resize(abc9_box_seq+1);
+                                       box_list[abc9_box_seq] = cell;
+                                       if (!inst_module->get_bool_attribute("\\abc9_flop"))
                                                continue;
                                }
 
@@ -542,6 +538,8 @@ struct XAigerWriter
 
                        int box_count = 0;
                        for (auto cell : box_list) {
+                               log_assert(cell);
+
                                RTLIL::Module* box_module = module->design->module(cell->type);
                                log_assert(box_module);
 
@@ -611,7 +609,7 @@ struct XAigerWriter
                        f.write(buffer_str.data(), buffer_str.size());
 
                        if (holes_module) {
-                               log_push();
+                               log_module(holes_module);
 
                                std::stringstream a_buffer;
                                XAigerWriter writer(holes_module);
@@ -622,8 +620,6 @@ struct XAigerWriter
                                int32_t buffer_size_be = to_big_endian(buffer_str.size());
                                f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
                                f.write(buffer_str.data(), buffer_str.size());
-
-                               log_pop();
                        }
                }
 

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 0da8158709ba66ae752fd02c319b0bc19303625a..d51ed33527348ecd39b146dc26e01ea21e7e9b2e 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -186,7 +186,10 @@ struct Abc9Pass : public ScriptPass
        void script() YS_OVERRIDE
        {
                run("scc -set_attr abc9_scc_id {}");
-               run("abc9_ops -break_scc -prep_holes");
+               if (help_mode)
+                       run("abc9_ops -break_scc -prep_holes [-dff]", "(option for -dff)");
+               else
+                       run("abc9_ops -break_scc -prep_holes" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
                run("select -set abc9_holes A:abc9_holes");
                run("flatten -wb @abc9_holes");
                run("techmap @abc9_holes");

diff --git a/passes/techmap/abc9_map.cc b/passes/techmap/abc9_map.cc
index 171289c6d45c215de82c7ee3bb6ef1a090a0a92d..d007dbcc272ab98f6be390c2e2c991fbcbbf7408 100644 (file)
--- a/passes/techmap/abc9_map.cc
+++ b/passes/techmap/abc9_map.cc
@@ -355,28 +355,14 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
                        if (markgroups) remap_wire->attributes[ID(abcgroup)] = map_autoidx;
                }
 
-               dict<IdString, bool> abc9_box;
                vector<RTLIL::Cell*> boxes;
                for (auto cell : cells) {
                        if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_))) {
                                module->remove(cell);
                                continue;
                        }
-                       auto jt = abc9_box.find(cell->type);
-                       if (jt == abc9_box.end()) {
-                               RTLIL::Module* box_module = design->module(cell->type);
-                               jt = abc9_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc9_box_id)))).first;
-                       }
-                       if (jt->second) {
-                               auto kt = cell->attributes.find("\\abc9_keep");
-                               bool abc9_keep = false;
-                               if (kt != cell->attributes.end()) {
-                                       abc9_keep = kt->second.as_bool();
-                                       cell->attributes.erase(kt);
-                               }
-                               if (!abc9_keep)
-                                       boxes.emplace_back(cell);
-                       }
+                       if (cell->attributes.erase("\\abc9_box_seq"))
+                               boxes.emplace_back(cell);
                }
 
                dict<SigBit, pool<IdString>> bit_drivers, bit_users;

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 2f07de8d433512780fa211f8698ef32bfe72e838..ab5aa9f8d15532858306ed8577bde7d0405d8db0 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -109,39 +109,31 @@ void prep_dff(RTLIL::Module *module)
        typedef SigSpec clkdomain_t;
        dict<clkdomain_t, int> clk_to_mergeability;
 
-       //if (dff_mode)
-               for (auto cell : module->selected_cells()) {
-                       if (cell->type != "$__ABC9_FF_")
-                               continue;
+       for (auto cell : module->selected_cells()) {
+               if (cell->type != "$__ABC9_FF_")
+                       continue;
 
-                       Wire *abc9_clock_wire = module->wire(stringf("%s.clock", cell->name.c_str()));
-                       if (abc9_clock_wire == NULL)
-                               log_error("'%s.clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
-                       SigSpec abc9_clock = assign_map(abc9_clock_wire);
-
-                       clkdomain_t key(abc9_clock);
-
-                       auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
-                       auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
-                       log_assert(r2.second);
-
-                       Wire *abc9_init_wire = module->wire(stringf("%s.init", cell->name.c_str()));
-                       if (abc9_init_wire == NULL)
-                               log_error("'%s.init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
-                       log_assert(GetSize(abc9_init_wire) == 1);
-                       SigSpec abc9_init = assign_map(abc9_init_wire);
-                       if (!abc9_init.is_fully_const())
-                               log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
-                       r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
-                       log_assert(r2.second);
-               }
-       //else
-       //      for (auto cell : module->selected_cells()) {
-       //              auto inst_module = design->module(cell->type);
-       //              if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop"))
-       //                      continue;
-       //              cell->set_bool_attribute("\\abc9_keep");
-       //      }
+               Wire *abc9_clock_wire = module->wire(stringf("%s.clock", cell->name.c_str()));
+               if (abc9_clock_wire == NULL)
+                       log_error("'%s.clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+               SigSpec abc9_clock = assign_map(abc9_clock_wire);
+
+               clkdomain_t key(abc9_clock);
+
+               auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
+               auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
+               log_assert(r2.second);
+
+               Wire *abc9_init_wire = module->wire(stringf("%s.init", cell->name.c_str()));
+               if (abc9_init_wire == NULL)
+                       log_error("'%s.init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+               log_assert(GetSize(abc9_init_wire) == 1);
+               SigSpec abc9_init = assign_map(abc9_init_wire);
+               if (!abc9_init.is_fully_const())
+                       log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+               r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
+               log_assert(r2.second);
+       }
 
        RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str()));
        if (holes_module) {
@@ -188,7 +180,7 @@ void prep_dff(RTLIL::Module *module)
        }
 }
 
-void prep_holes(RTLIL::Module *module)
+void prep_holes(RTLIL::Module *module, bool dff)
 {
        auto design = module->design;
        log_assert(design);
@@ -204,10 +196,15 @@ void prep_holes(RTLIL::Module *module)
                        continue;
 
                auto inst_module = module->design->module(cell->type);
-               bool abc9_box = inst_module && inst_module->attributes.count("\\abc9_box_id") && !cell->get_bool_attribute("\\abc9_keep");
-               abc9_box_seen = abc9_box_seen || abc9_box;
-
-               if (!abc9_box && !yosys_celltypes.cell_known(cell->type))
+               bool abc9_box = inst_module && inst_module->attributes.count("\\abc9_box_id");
+               bool abc9_flop = false;
+               if (abc9_box) {
+                       abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
+                       if (abc9_flop && !dff)
+                               continue;
+                       abc9_box_seen = abc9_box;
+               }
+               else if (!yosys_celltypes.cell_known(cell->type))
                        continue;
 
                for (auto conn : cell->connections()) {
@@ -215,7 +212,7 @@ void prep_holes(RTLIL::Module *module)
                                for (auto bit : sigmap(conn.second))
                                        bit_users[bit].insert(cell->name);
 
-                       if (cell->output(conn.first))
+                       if (cell->output(conn.first) && !abc9_flop)
                                for (auto bit : sigmap(conn.second))
                                        bit_drivers[bit].insert(cell->name);
                }
@@ -255,8 +252,7 @@ void prep_holes(RTLIL::Module *module)
                log_assert(cell);
 
                RTLIL::Module* box_module = design->module(cell->type);
-               if (!box_module || !box_module->attributes.count("\\abc9_box_id")
-                               || cell->get_bool_attribute("\\abc9_keep"))
+               if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
                        continue;
 
                bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
@@ -297,7 +293,7 @@ void prep_holes(RTLIL::Module *module)
                        }
                }
 
-               cell->attributes["\\abc9_box_order"] = box_list.size();
+               cell->attributes["\\abc9_box_seq"] = box_list.size();
                box_list.emplace_back(cell);
        }
        log_assert(!box_list.empty());
@@ -437,6 +433,7 @@ struct Abc9OpsPass : public Pass {
                bool unbreak_scc_mode = false;
                bool prep_dff_mode = false;
                bool prep_holes_mode = false;
+               bool dff_mode = false;
 
                size_t argidx;
                for (argidx = 1; argidx < args.size(); argidx++) {
@@ -457,6 +454,10 @@ struct Abc9OpsPass : public Pass {
                                prep_holes_mode = true;
                                continue;
                        }
+                       if (arg == "-dff") {
+                               dff_mode = true;
+                               continue;
+                       }
                        break;
                }
                extra_args(args, argidx, design);
@@ -479,7 +480,7 @@ struct Abc9OpsPass : public Pass {
                        if (prep_dff_mode)
                                prep_dff(mod);
                        if (prep_holes_mode)
-                               prep_holes(mod);
+                               prep_holes(mod, dff_mode);
                }
        }
 } Abc9OpsPass;