add images

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index c100bdf41b57a1db6b54c55ccaa9d97012c089eb..b2e3c92c084a6e66b4ccf93051fed82486b02ac0 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -241,7 +241,7 @@
    \item Predication in INT regs as a BIT field (max VL=XLEN)
    \item Minimum VL must be Num Regs - 1 (all regs single LD/ST)
    \item SV may condense sparse Vecs: RVV lets ALU do predication
-   \item NO ZEROING: non-predicated elements are skipped
+   \item Choice to Zero or skip non-predicated elements
   \end{itemize}
 }