as SVP64, instructions may be issued `madded r20,r4,r8,r20
madded r21,r5,r9,r21` etc. where the first `madded` will have
stored the upper half of the 128-bit multiply into r21, such
-that it may be picked up by the second `madded`.*
+that it may be picked up by the second `madded`. Repeat inline
+to construct a larger bigint scalar-vector multiply,
+as Scalar GPR register file space permits.*
SVP64 overrides the Scalar behaviour of what defines RS.
For SVP64 EXTRA register extension, the `RM-1P-3S-1D` format is