soc_core: add back identifier

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 43a03bfff0b93c0f110f27bc96380b0d9114e99a..247685bc8514501631bc5b4557cc3f06b6f0015c 100755 (executable)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -881,7 +881,7 @@ class LiteXSoC(SoC):
         self.check_if_exists(name)
         if with_build_time:
             identifier += " " + build_time()
-        setattr(self.submodules, name, Identifier(ident))
+        setattr(self.submodules, name, Identifier(identifier))
         self.csr.add(name + "_mem", use_loc_if_exists=True)
 
     # Add UART -------------------------------------------------------------------------------------

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 0d59924e344758ebaf8b527d67937389908382d1..d58b9f0fe631b3d8396708b756bc7288b7d86d3b 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -169,6 +169,10 @@ class SoCCore(LiteXSoC):
         if integrated_main_ram_size:
             self.add_ram("main_ram", self.mem_map["main_ram"], integrated_main_ram_size)
 
+        # Add Identifier
+        if ident != "":
+            self.add_identifier("identifier", identifier=ident, with_build_time=ident_version)
+
         # Add UART
         if with_uart:
             self.add_uart(name=uart_name, baudrate=uart_baudrate)