(no commit message)

diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn
index 55e7ad6c8f8615a0627c8d01873a0d46bcdfaeb5..719755e348e35f48d8e1617cd1d481d2e7eb8c6d 100644 (file)
--- a/openpower/sv/biginteger/analysis.mdwn
+++ b/openpower/sv/biginteger/analysis.mdwn
@@ -282,8 +282,8 @@ With effectively 5 operands (3 in, 2 out) some compromises are needed.
 A little though gives a useful workaround: two modes,
 controlled by a single bit in `RM.EXTRA`, determine whether the 5th
 register is set to RC or whether to RT+VL. This then leaves only
-4 registers to qualify as scalar/vector, and this can use four
-EXTRA2 designators which fits into the available space.
+4 registers to qualify as scalar/vector, which can use four
+EXTRA2 designators and fits into the available 9-bit space.
 
 RS=RT+VL Mode: