--- /dev/null
+//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//==-----------------------------------------------------------------------===//
+// This file specifies where the base TD file exists
+// and where the version specific TD file exists.
+include "AMDILBase.td"
+include "AMDILVersion.td"
+
+include "R600Schedule.td"
+include "SISchedule.td"
+include "Processors.td"
+include "AMDGPUInstrInfo.td"
+include "AMDGPUIntrinsics.td"
+include "AMDGPURegisterInfo.td"
+include "AMDGPUInstructions.td"
} // end namespace llvm;
#define GET_REGINFO_ENUM
-#include "AMDILGenRegisterInfo.inc"
+#include "AMDGPUGenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM
-#include "AMDILGenInstrInfo.inc"
+#include "AMDGPUGenInstrInfo.inc"
/// Include device information enumerations
#include "AMDILDeviceInfo.h"
+++ /dev/null
-//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//==-----------------------------------------------------------------------===//
-// This file specifies where the base TD file exists
-// and where the version specific TD file exists.
-include "AMDILBase.td"
-include "AMDILVersion.td"
-
-include "R600Schedule.td"
-include "SISchedule.td"
-include "Processors.td"
-include "AMDGPUInstrInfo.td"
-include "AMDGPUIntrinsics.td"
-include "AMDGPURegisterInfo.td"
-include "AMDGPUInstructions.td"
bool SelectADDRReg(SDValue Addr, SDValue& Base, SDValue& Offset);
// Include the pieces autogenerated from the target description.
-#include "AMDILGenDAGISel.inc"
+#include "AMDGPUGenDAGISel.inc"
};
} // end anonymous namespace
//===----------------------------------------------------------------------===//
// Calling Convention Implementation
//===----------------------------------------------------------------------===//
-#include "AMDILGenCallingConv.inc"
+#include "AMDGPUGenCallingConv.inc"
//===----------------------------------------------------------------------===//
// TargetLowering Implementation Help Functions Begin
#include "llvm/Instructions.h"
#define GET_INSTRINFO_CTOR
-#include "AMDILGenInstrInfo.inc"
+#include "AMDGPUGenInstrInfo.inc"
using namespace llvm;
#include "llvm/Target/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
-#include "AMDILGenInstrInfo.inc"
+#include "AMDGPUGenInstrInfo.inc"
namespace llvm {
// AMDIL - This namespace holds all of the target specific flags that
using namespace llvm;
#define GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN
-#include "AMDILGenIntrinsics.inc"
+#include "AMDGPUGenIntrinsics.inc"
#undef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN
AMDILIntrinsicInfo::AMDILIntrinsicInfo(TargetMachine *tm)
{
static const char* const names[] = {
#define GET_INTRINSIC_NAME_TABLE
-#include "AMDILGenIntrinsics.inc"
+#include "AMDGPUGenIntrinsics.inc"
#undef GET_INTRINSIC_NAME_TABLE
};
AMDILIntrinsicInfo::lookupName(const char *Name, unsigned int Len) const
{
#define GET_FUNCTION_RECOGNIZER
-#include "AMDILGenIntrinsics.inc"
+#include "AMDGPUGenIntrinsics.inc"
#undef GET_FUNCTION_RECOGNIZER
AMDGPUIntrinsic::ID IntrinsicID
= (AMDGPUIntrinsic::ID)Intrinsic::not_intrinsic;
{
// Overload Table
#define GET_INTRINSIC_OVERLOAD_TABLE
-#include "AMDILGenIntrinsics.inc"
+#include "AMDGPUGenIntrinsics.inc"
#undef GET_INTRINSIC_OVERLOAD_TABLE
}
/// This defines the "getAttributes(ID id)" method.
#define GET_INTRINSIC_ATTRIBUTES
-#include "AMDILGenIntrinsics.inc"
+#include "AMDGPUGenIntrinsics.inc"
#undef GET_INTRINSIC_ATTRIBUTES
Function*
enum ID {
last_non_AMDIL_intrinsic = Intrinsic::num_intrinsics - 1,
#define GET_INTRINSIC_ENUM_VALUES
-#include "AMDILGenIntrinsics.inc"
+#include "AMDGPUGenIntrinsics.inc"
#undef GET_INTRINSIC_ENUM_VALUES
, num_AMDIL_intrinsics
};
}
#define GET_REGINFO_TARGET_DESC
-#include "AMDILGenRegisterInfo.inc"
+#include "AMDGPUGenRegisterInfo.inc"
#include "llvm/Target/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
-#include "AMDILGenRegisterInfo.inc"
+#include "AMDGPUGenRegisterInfo.inc"
// See header file for explanation
namespace llvm
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_TARGET_DESC
-#include "AMDILGenSubtargetInfo.inc"
+#include "AMDGPUGenSubtargetInfo.inc"
AMDILSubtarget::AMDILSubtarget(llvm::StringRef TT, llvm::StringRef CPU, llvm::StringRef FS) : AMDILGenSubtargetInfo( TT, CPU, FS ),
mDumpCode(false)
#include <string>
#define GET_SUBTARGETINFO_HEADER
-#include "AMDILGenSubtargetInfo.inc"
+#include "AMDGPUGenSubtargetInfo.inc"
#define MAX_CB_SIZE (1 << 16)
namespace llvm {
#include "llvm/Support/TargetRegistry.h"
#define GET_INSTRINFO_MC_DESC
-#include "AMDILGenInstrInfo.inc"
+#include "AMDGPUGenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC
-#include "AMDILGenSubtargetInfo.inc"
+#include "AMDGPUGenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC
-#include "AMDILGenRegisterInfo.inc"
+#include "AMDGPUGenRegisterInfo.inc"
using namespace llvm;
} // End llvm namespace
#define GET_REGINFO_ENUM
-#include "AMDILGenRegisterInfo.inc"
+#include "AMDGPUGenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM
-#include "AMDILGenInstrInfo.inc"
+#include "AMDGPUGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
-#include "AMDILGenSubtargetInfo.inc"
+#include "AMDGPUGenSubtargetInfo.inc"
#endif // AMDILMCTARGETDESC_H
R600RegisterInfo.td: R600GenRegisterInfo.pl
$(PERL) $^ > $@
-AMDILGenRegisterInfo.inc: *.td
- $(call tablegen, -gen-register-info, AMDIL.td, $@)
+AMDGPUGenRegisterInfo.inc: *.td
+ $(call tablegen, -gen-register-info, AMDGPU.td, $@)
-AMDILGenInstrInfo.inc: *.td
- $(call tablegen, -gen-instr-info, AMDIL.td, $@)
+AMDGPUGenInstrInfo.inc: *.td
+ $(call tablegen, -gen-instr-info, AMDGPU.td, $@)
-AMDILGenAsmWriter.inc: *.td
- $(call tablegen, -gen-asm-writer, AMDIL.td, $@)
+AMDGPUGenAsmWriter.inc: *.td
+ $(call tablegen, -gen-asm-writer, AMDGPU.td, $@)
-AMDILGenDAGISel.inc: *.td
- $(call tablegen, -gen-dag-isel, AMDIL.td, $@)
+AMDGPUGenDAGISel.inc: *.td
+ $(call tablegen, -gen-dag-isel, AMDGPU.td, $@)
-AMDILGenCallingConv.inc: *.td
- $(call tablegen, -gen-callingconv, AMDIL.td, $@)
+AMDGPUGenCallingConv.inc: *.td
+ $(call tablegen, -gen-callingconv, AMDGPU.td, $@)
-AMDILGenSubtargetInfo.inc: *.td
- $(call tablegen, -gen-subtarget, AMDIL.td, $@)
+AMDGPUGenSubtargetInfo.inc: *.td
+ $(call tablegen, -gen-subtarget, AMDGPU.td, $@)
-AMDILGenEDInfo.inc: *.td
- $(call tablegen, -gen-enhanced-disassembly-info, AMDIL.td, $@)
+AMDGPUGenEDInfo.inc: *.td
+ $(call tablegen, -gen-enhanced-disassembly-info, AMDGPU.td, $@)
-AMDILGenIntrinsics.inc: *.td
- $(call tablegen, -gen-tgt-intrinsic, AMDIL.td, $@)
+AMDGPUGenIntrinsics.inc: *.td
+ $(call tablegen, -gen-tgt-intrinsic, AMDGPU.td, $@)
-AMDILGenCodeEmitter.inc: *.td
- $(call tablegen, -gen-emitter, AMDIL.td, $@)
+AMDGPUGenCodeEmitter.inc: *.td
+ $(call tablegen, -gen-emitter, AMDGPU.td, $@)
LOADER_LIBS=$(shell llvm-config --libs bitreader asmparser)
loader: loader.o libradeon.a
R600RegisterInfo.td \
SIRegisterInfo.td \
SIRegisterGetHWRegNum.inc \
- AMDILGenRegisterInfo.inc \
- AMDILGenInstrInfo.inc \
- AMDILGenAsmWriter.inc \
- AMDILGenDAGISel.inc \
- AMDILGenCallingConv.inc \
- AMDILGenSubtargetInfo.inc \
- AMDILGenEDInfo.inc \
- AMDILGenIntrinsics.inc \
- AMDILGenCodeEmitter.inc
+ AMDGPUGenRegisterInfo.inc \
+ AMDGPUGenInstrInfo.inc \
+ AMDGPUGenAsmWriter.inc \
+ AMDGPUGenDAGISel.inc \
+ AMDGPUGenCallingConv.inc \
+ AMDGPUGenSubtargetInfo.inc \
+ AMDGPUGenEDInfo.inc \
+ AMDGPUGenIntrinsics.inc \
+ AMDGPUGenCodeEmitter.inc
CPP_SOURCES := \
AMDIL7XXDevice.cpp \
}
}
-#include "AMDILGenCodeEmitter.inc"
+#include "AMDGPUGenCodeEmitter.inc"