radeon/llvm: Change prefix on tablegen files to AMDGPU
authorTom Stellard <thomas.stellard@amd.com>
Wed, 30 May 2012 23:23:39 +0000 (19:23 -0400)
committerTom Stellard <thomas.stellard@amd.com>
Fri, 1 Jun 2012 15:28:11 +0000 (11:28 -0400)
18 files changed:
src/gallium/drivers/radeon/AMDGPU.td [new file with mode: 0644]
src/gallium/drivers/radeon/AMDIL.h
src/gallium/drivers/radeon/AMDIL.td [deleted file]
src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp
src/gallium/drivers/radeon/AMDILISelLowering.cpp
src/gallium/drivers/radeon/AMDILInstrInfo.cpp
src/gallium/drivers/radeon/AMDILInstrInfo.h
src/gallium/drivers/radeon/AMDILIntrinsicInfo.cpp
src/gallium/drivers/radeon/AMDILIntrinsicInfo.h
src/gallium/drivers/radeon/AMDILRegisterInfo.cpp
src/gallium/drivers/radeon/AMDILRegisterInfo.h
src/gallium/drivers/radeon/AMDILSubtarget.cpp
src/gallium/drivers/radeon/AMDILSubtarget.h
src/gallium/drivers/radeon/MCTargetDesc/AMDILMCTargetDesc.cpp
src/gallium/drivers/radeon/MCTargetDesc/AMDILMCTargetDesc.h
src/gallium/drivers/radeon/Makefile
src/gallium/drivers/radeon/Makefile.sources
src/gallium/drivers/radeon/R600CodeEmitter.cpp

diff --git a/src/gallium/drivers/radeon/AMDGPU.td b/src/gallium/drivers/radeon/AMDGPU.td
new file mode 100644 (file)
index 0000000..28d4182
--- /dev/null
@@ -0,0 +1,20 @@
+//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//==-----------------------------------------------------------------------===//
+// This file specifies where the base TD file exists
+// and where the version specific TD file exists.
+include "AMDILBase.td"
+include "AMDILVersion.td"
+
+include "R600Schedule.td"
+include "SISchedule.td"
+include "Processors.td"
+include "AMDGPUInstrInfo.td"
+include "AMDGPUIntrinsics.td"
+include "AMDGPURegisterInfo.td"
+include "AMDGPUInstructions.td"
index 8bd024a4bd8d95a068cef682411c7dd142150d2f..4029f2780db8167865897d3ab20cd4c2637182c9 100644 (file)
@@ -105,9 +105,9 @@ extern Target TheAMDGPUTarget;
 } // end namespace llvm;
 
 #define GET_REGINFO_ENUM
-#include "AMDILGenRegisterInfo.inc"
+#include "AMDGPUGenRegisterInfo.inc"
 #define GET_INSTRINFO_ENUM
-#include "AMDILGenInstrInfo.inc"
+#include "AMDGPUGenInstrInfo.inc"
 
 /// Include device information enumerations
 #include "AMDILDeviceInfo.h"
diff --git a/src/gallium/drivers/radeon/AMDIL.td b/src/gallium/drivers/radeon/AMDIL.td
deleted file mode 100644 (file)
index 28d4182..0000000
+++ /dev/null
@@ -1,20 +0,0 @@
-//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//==-----------------------------------------------------------------------===//
-// This file specifies where the base TD file exists
-// and where the version specific TD file exists.
-include "AMDILBase.td"
-include "AMDILVersion.td"
-
-include "R600Schedule.td"
-include "SISchedule.td"
-include "Processors.td"
-include "AMDGPUInstrInfo.td"
-include "AMDGPUIntrinsics.td"
-include "AMDGPURegisterInfo.td"
-include "AMDGPUInstructions.td"
index 40b35fd45decc80d19b74dbf76f114a231994730..b14a360c3ccdd91410ee8a57c0e898a010578e5e 100644 (file)
@@ -71,7 +71,7 @@ private:
   bool SelectADDRReg(SDValue Addr, SDValue& Base, SDValue& Offset);
 
   // Include the pieces autogenerated from the target description.
-#include "AMDILGenDAGISel.inc"
+#include "AMDGPUGenDAGISel.inc"
 };
 }  // end anonymous namespace
 
index a52c83e5790462cc9eb50991a1a3f080afb92947..afb9170cdd2a57dfbf47add3bf7d272103726c3a 100644 (file)
@@ -38,7 +38,7 @@ using namespace llvm;
 //===----------------------------------------------------------------------===//
 // Calling Convention Implementation
 //===----------------------------------------------------------------------===//
-#include "AMDILGenCallingConv.inc"
+#include "AMDGPUGenCallingConv.inc"
 
 //===----------------------------------------------------------------------===//
 // TargetLowering Implementation Help Functions Begin
index 0ac56b5186d468cf3e8d812867f9fd8801c204c5..5143f3fd8fc7def0903f41048259ce7bc56f9856 100644 (file)
@@ -22,7 +22,7 @@
 #include "llvm/Instructions.h"
 
 #define GET_INSTRINFO_CTOR
-#include "AMDILGenInstrInfo.inc"
+#include "AMDGPUGenInstrInfo.inc"
 
 using namespace llvm;
 
index 9de16ed8e59165c7b8846eaba6c2c42f62bff65f..6aa03e713ae371d80f841e5aac31407de034b9d4 100644 (file)
@@ -18,7 +18,7 @@
 #include "llvm/Target/TargetInstrInfo.h"
 
 #define GET_INSTRINFO_HEADER
-#include "AMDILGenInstrInfo.inc"
+#include "AMDGPUGenInstrInfo.inc"
 
 namespace llvm {
   // AMDIL - This namespace holds all of the target specific flags that
index 651c0549413f9778fed5a4c24eca0d1474e61ed7..678e32e8d10f06afd5ccc2b9e2e70f0fe8c401b8 100644 (file)
@@ -21,7 +21,7 @@
 using namespace llvm;
 
 #define GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN
-#include "AMDILGenIntrinsics.inc"
+#include "AMDGPUGenIntrinsics.inc"
 #undef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN
 
 AMDILIntrinsicInfo::AMDILIntrinsicInfo(TargetMachine *tm) 
@@ -35,7 +35,7 @@ AMDILIntrinsicInfo::getName(unsigned int IntrID, Type **Tys,
 {
   static const char* const names[] = {
 #define GET_INTRINSIC_NAME_TABLE
-#include "AMDILGenIntrinsics.inc"
+#include "AMDGPUGenIntrinsics.inc"
 #undef GET_INTRINSIC_NAME_TABLE
   };
 
@@ -107,7 +107,7 @@ unsigned int
 AMDILIntrinsicInfo::lookupName(const char *Name, unsigned int Len) const 
 {
 #define GET_FUNCTION_RECOGNIZER
-#include "AMDILGenIntrinsics.inc"
+#include "AMDGPUGenIntrinsics.inc"
 #undef GET_FUNCTION_RECOGNIZER
   AMDGPUIntrinsic::ID IntrinsicID
     = (AMDGPUIntrinsic::ID)Intrinsic::not_intrinsic;
@@ -132,13 +132,13 @@ AMDILIntrinsicInfo::isOverloaded(unsigned id) const
 {
   // Overload Table
 #define GET_INTRINSIC_OVERLOAD_TABLE
-#include "AMDILGenIntrinsics.inc"
+#include "AMDGPUGenIntrinsics.inc"
 #undef GET_INTRINSIC_OVERLOAD_TABLE
 }
 
 /// This defines the "getAttributes(ID id)" method.
 #define GET_INTRINSIC_ATTRIBUTES
-#include "AMDILGenIntrinsics.inc"
+#include "AMDGPUGenIntrinsics.inc"
 #undef GET_INTRINSIC_ATTRIBUTES
 
 Function*
index bdd0366fd1cd122f90077c69ef5565361689bb8f..072c26531d19508788dff57a10d67b11992d2e56 100644 (file)
@@ -22,7 +22,7 @@ namespace llvm {
     enum ID {
       last_non_AMDIL_intrinsic = Intrinsic::num_intrinsics - 1,
 #define GET_INTRINSIC_ENUM_VALUES
-#include "AMDILGenIntrinsics.inc"
+#include "AMDGPUGenIntrinsics.inc"
 #undef GET_INTRINSIC_ENUM_VALUES
       , num_AMDIL_intrinsics
     };
index 9d93b91f0001cd6c8f22ae9f7810d9b1b9b97d4c..af2113b1526f538e7e15eb62fd859f215b9f47a4 100644 (file)
@@ -198,5 +198,5 @@ AMDILRegisterInfo::getStackSize() const
 }
 
 #define GET_REGINFO_TARGET_DESC
-#include "AMDILGenRegisterInfo.inc"
+#include "AMDGPUGenRegisterInfo.inc"
 
index 8dd4281d6a52bd6c10f288308177b0c4a6573e22..7627bdec0458c8438f4ba39814bf91fdbac5de15 100644 (file)
@@ -17,7 +17,7 @@
 #include "llvm/Target/TargetRegisterInfo.h"
 
 #define GET_REGINFO_HEADER
-#include "AMDILGenRegisterInfo.inc"
+#include "AMDGPUGenRegisterInfo.inc"
 // See header file for explanation
 
 namespace llvm
index 249cb03f4a3b83c6d2e14b34bf9dc48a4e958426..723037e2e723e20e6a702696313a07d90dba5b5f 100644 (file)
@@ -25,7 +25,7 @@ using namespace llvm;
 #define GET_SUBTARGETINFO_ENUM
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "AMDILGenSubtargetInfo.inc"
+#include "AMDGPUGenSubtargetInfo.inc"
 
 AMDILSubtarget::AMDILSubtarget(llvm::StringRef TT, llvm::StringRef CPU, llvm::StringRef FS) : AMDILGenSubtargetInfo( TT, CPU, FS ),
   mDumpCode(false)
index 38fcb859ac643af932d5d6e11ca2150c11a57ce2..e3d8c814d0a18a7c08eb5684fe9dcd5d19faf615 100644 (file)
@@ -22,7 +22,7 @@
 #include <string>
 
 #define GET_SUBTARGETINFO_HEADER
-#include "AMDILGenSubtargetInfo.inc"
+#include "AMDGPUGenSubtargetInfo.inc"
 
 #define MAX_CB_SIZE (1 << 16)
 namespace llvm {
index 3488d708e8c0202521dce1b80fff121411b85987..52c5faa6930b26b9d205c38bfc7379d2fed14860 100644 (file)
@@ -9,13 +9,13 @@
 #include "llvm/Support/TargetRegistry.h"
 
 #define GET_INSTRINFO_MC_DESC
-#include "AMDILGenInstrInfo.inc"
+#include "AMDGPUGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
-#include "AMDILGenSubtargetInfo.inc"
+#include "AMDGPUGenSubtargetInfo.inc"
 
 #define GET_REGINFO_MC_DESC
-#include "AMDILGenRegisterInfo.inc"
+#include "AMDGPUGenRegisterInfo.inc"
 
 using namespace llvm;
 
index 8951a4e6461f73df16bda57e8d72185195f743e9..2eab136e67a2133e2fbb7927a4a5974a718358b9 100644 (file)
@@ -24,12 +24,12 @@ extern Target TheAMDGPUTarget;
 } // End llvm namespace
 
 #define GET_REGINFO_ENUM
-#include "AMDILGenRegisterInfo.inc"
+#include "AMDGPUGenRegisterInfo.inc"
 
 #define GET_INSTRINFO_ENUM
-#include "AMDILGenInstrInfo.inc"
+#include "AMDGPUGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_ENUM
-#include "AMDILGenSubtargetInfo.inc"
+#include "AMDGPUGenSubtargetInfo.inc"
 
 #endif // AMDILMCTARGETDESC_H
index 3f930cd2784e61416522b7149b8f0e6512ce7125..db5dbaa0819fc66a3eccfdf423fad5aa47a9d08a 100644 (file)
@@ -38,32 +38,32 @@ endif
 R600RegisterInfo.td: R600GenRegisterInfo.pl
        $(PERL) $^ > $@
 
-AMDILGenRegisterInfo.inc: *.td
-       $(call tablegen, -gen-register-info, AMDIL.td, $@)
+AMDGPUGenRegisterInfo.inc: *.td
+       $(call tablegen, -gen-register-info, AMDGPU.td, $@)
 
-AMDILGenInstrInfo.inc: *.td
-       $(call tablegen, -gen-instr-info, AMDIL.td, $@)
+AMDGPUGenInstrInfo.inc: *.td
+       $(call tablegen, -gen-instr-info, AMDGPU.td, $@)
 
-AMDILGenAsmWriter.inc: *.td
-       $(call tablegen, -gen-asm-writer, AMDIL.td, $@)
+AMDGPUGenAsmWriter.inc: *.td
+       $(call tablegen, -gen-asm-writer, AMDGPU.td, $@)
 
-AMDILGenDAGISel.inc: *.td
-       $(call tablegen, -gen-dag-isel, AMDIL.td, $@)
+AMDGPUGenDAGISel.inc: *.td
+       $(call tablegen, -gen-dag-isel, AMDGPU.td, $@)
 
-AMDILGenCallingConv.inc: *.td
-       $(call tablegen, -gen-callingconv, AMDIL.td, $@)
+AMDGPUGenCallingConv.inc: *.td
+       $(call tablegen, -gen-callingconv, AMDGPU.td, $@)
 
-AMDILGenSubtargetInfo.inc: *.td
-       $(call tablegen, -gen-subtarget, AMDIL.td, $@)
+AMDGPUGenSubtargetInfo.inc: *.td
+       $(call tablegen, -gen-subtarget, AMDGPU.td, $@)
 
-AMDILGenEDInfo.inc: *.td
-       $(call tablegen, -gen-enhanced-disassembly-info, AMDIL.td, $@)
+AMDGPUGenEDInfo.inc: *.td
+       $(call tablegen, -gen-enhanced-disassembly-info, AMDGPU.td, $@)
 
-AMDILGenIntrinsics.inc: *.td
-       $(call tablegen, -gen-tgt-intrinsic, AMDIL.td, $@)
+AMDGPUGenIntrinsics.inc: *.td
+       $(call tablegen, -gen-tgt-intrinsic, AMDGPU.td, $@)
 
-AMDILGenCodeEmitter.inc: *.td
-       $(call tablegen, -gen-emitter, AMDIL.td, $@)
+AMDGPUGenCodeEmitter.inc: *.td
+       $(call tablegen, -gen-emitter, AMDGPU.td, $@)
 
 LOADER_LIBS=$(shell llvm-config --libs bitreader asmparser)
 loader: loader.o libradeon.a
index 51eb3aecb4f10aae8e8d579397bbf766bbbf144b..7ba09802b6d0b45ed122d5243f0fa430cd23f97f 100644 (file)
@@ -4,15 +4,15 @@ GENERATED_SOURCES := \
        R600RegisterInfo.td             \
        SIRegisterInfo.td               \
        SIRegisterGetHWRegNum.inc               \
-       AMDILGenRegisterInfo.inc        \
-       AMDILGenInstrInfo.inc           \
-       AMDILGenAsmWriter.inc           \
-       AMDILGenDAGISel.inc             \
-       AMDILGenCallingConv.inc         \
-       AMDILGenSubtargetInfo.inc               \
-       AMDILGenEDInfo.inc              \
-       AMDILGenIntrinsics.inc          \
-       AMDILGenCodeEmitter.inc
+       AMDGPUGenRegisterInfo.inc       \
+       AMDGPUGenInstrInfo.inc          \
+       AMDGPUGenAsmWriter.inc          \
+       AMDGPUGenDAGISel.inc            \
+       AMDGPUGenCallingConv.inc                \
+       AMDGPUGenSubtargetInfo.inc              \
+       AMDGPUGenEDInfo.inc             \
+       AMDGPUGenIntrinsics.inc         \
+       AMDGPUGenCodeEmitter.inc
 
 CPP_SOURCES := \
        AMDIL7XXDevice.cpp              \
index e8d0efefff5df23528f57fe39d6be87d702a4daa..fdc79a674991e6c61c8fe065b550b086ea27066a 100644 (file)
@@ -654,5 +654,5 @@ uint64_t R600CodeEmitter::getMachineOpValue(const MachineInstr &MI,
   }
 }
 
-#include "AMDILGenCodeEmitter.inc"
+#include "AMDGPUGenCodeEmitter.inc"