fix bitwidth issues for rv32 in mulh* and sra

diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
index d7a95e9ae98d513f7b70079a08be8b00ad6ab8a3..7578ae6c0effbd9bda8f70fa4d831586219f2b38 100644 (file)
--- a/riscv/insns/mulh.h
+++ b/riscv/insns/mulh.h
@@ -2,5 +2,4 @@ require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulh(RS1, RS2));
 else
-  WRITE_RD(sext32(rv_sr(rv_mul(sext32(RS1), sext32(RS2)),
-                        sv_reg_t(32U))));
+  WRITE_RD(sext32(rv_mulh(sext32(RS1), sext32(RS2))));

diff --git a/riscv/insns/mulhsu.h b/riscv/insns/mulhsu.h
index 724e66170c62f92efc7ad0ebb2248736413f1841..752189985a6fd87fa7d7a821f2aa5eadcf1f8ce1 100644 (file)
--- a/riscv/insns/mulhsu.h
+++ b/riscv/insns/mulhsu.h
@@ -2,5 +2,4 @@ require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulhsu(RS1, RS2));
 else
-  WRITE_RD(sext32(rv_sr((rv_mul(sext32(RS1), sv_reg_uint32(RS2))),
-                  sv_reg_t(32U))));
+  WRITE_RD(sext32((rv_mulhsu(sext32(RS1), sv_reg_uint32(RS2)))));

diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h
index dee66b05e29e3955cf2af05353bc7b68fab668e2..dcfc2434e5ebf664bb29ee303fb1c41c6a60de8b 100644 (file)
--- a/riscv/insns/mulhu.h
+++ b/riscv/insns/mulhu.h
@@ -2,6 +2,4 @@ require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulhu(RS1, RS2));
 else
-  WRITE_RD(sext32(rv_sr(rv_mul(sv_reg_uint32(RS1),
-                          sv_reg_uint32(RS2)),
-                        sv_reg_t(32U))));
+  WRITE_RD(sext32(rv_mulhu(sv_reg_uint32(RS1), sv_reg_uint32(RS2))));

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 6467e34085a63f6880395a8fe6fec69a923f5506..d3461163ae7331417b39c2477d23f4022384d2e8 100644 (file)
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -436,6 +436,9 @@ bool sv_proc_t::rv_int_op_prepare(SLHSTYPE const & lhs, SRHSTYPE const & rhs, \
                                  uint8_t &bitwidth) \
 {                                                                   \
     bitwidth = _insn->src_bitwidth;                                        \
+    if (bitwidth == 0) { \
+        bitwidth = xlen; \
+    } \
     if (bitwidth == xlen) {                                                \
         return true;                                                       \
     }                                                                   \
@@ -568,6 +571,21 @@ sv_sreg_t sv_proc_t::rv_mul(sv_sreg_t const & lhs, sv_sreg_t const & rhs)
     return lhs * rhs;
 }
 
+sv_reg_t sv_proc_t::rv_mulhu(sv_reg_t const & lhs, sv_reg_t const & rhs)
+{
+    return (lhs * rhs) >> 32;
+}
+
+sv_sreg_t sv_proc_t::rv_mulhsu(sv_sreg_t const & lhs, sv_reg_t const & rhs)
+{
+    return (lhs * rhs) >> 32;
+}
+
+sv_sreg_t sv_proc_t::rv_mulh(sv_sreg_t const & lhs, sv_sreg_t const & rhs)
+{
+    return (lhs * rhs) >> 32;
+}
+
 sv_reg_t sv_proc_t::rv_and(sv_reg_t const & lhs, sv_reg_t const & rhs)
 {
     return lhs & rhs;

diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 28659affb97011e29b5d2b847682743d1632349b..4056c5fa0dd0470bd4895469048264cd353680b5 100644 (file)
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -130,6 +130,9 @@ public:
     sv_reg_t rv_mul(sv_reg_t const & lhs, sv_reg_t const & rhs);
     sv_sreg_t rv_mul(sv_sreg_t const & lhs, sv_reg_t const & rhs);
     sv_sreg_t rv_mul(sv_sreg_t const & lhs, sv_sreg_t const & rhs);
+    sv_reg_t rv_mulhu(sv_reg_t const & lhs, sv_reg_t const & rhs);
+    sv_sreg_t rv_mulh(sv_sreg_t const & lhs, sv_sreg_t const & rhs);
+    sv_sreg_t rv_mulhsu(sv_sreg_t const & lhs, sv_reg_t const & rhs);
     sv_reg_t rv_and(sv_reg_t const & lhs, sv_reg_t const & rhs);
     sv_reg_t rv_or(sv_reg_t const & lhs, sv_reg_t const & rhs);
     sv_reg_t rv_xor(sv_reg_t const & lhs, sv_reg_t const & rhs);