radv: add has_clear_state and enable it on CIK+ only
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Thu, 5 Oct 2017 12:55:24 +0000 (14:55 +0200)
committerSamuel Pitoiset <samuel.pitoiset@gmail.com>
Thu, 12 Oct 2017 07:17:40 +0000 (09:17 +0200)
This will allow us to emit the CLEAR_STATE packet instead
of a bunch of useless packets when doing CS initialization.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
src/amd/vulkan/radv_device.c
src/amd/vulkan/radv_private.h

index 23f5e70321da16098f309c62da5013dfcac16ab5..b2aef2a8130ea57014bb7e6bb2d37c0533190c43 100644 (file)
@@ -401,6 +401,11 @@ radv_physical_device_init(struct radv_physical_device *device,
                device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
        }
 
+       /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
+        * on SI.
+        */
+       device->has_clear_state = device->rad_info.chip_class >= CIK;
+
        return VK_SUCCESS;
 
 fail:
index e673527811f612f35e864283f767190926342411..e58fb2175e279c971cdcb6d52b8ae28f6a4173ee 100644 (file)
@@ -277,7 +277,7 @@ struct radv_physical_device {
 
        bool has_rbplus; /* if RB+ register exist */
        bool rbplus_allowed; /* if RB+ is allowed */
-
+       bool has_clear_state;
 
        /* This is the drivers on-disk cache used as a fallback as opposed to
         * the pipeline cache defined by apps.