Add DSP_SIGNEDONLY back

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 5ff0e03aa58135f27dfea31dc7659a8bbd5e047c..6cd5128a602f5186ad866acdbb25e330885f589c 100644 (file)
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -55,6 +55,22 @@ module \$mul (A, B, Y);
        if (A_SIGNED != B_SIGNED)\r
                wire _TECHMAP_FAIL_ = 1;\r
        // NB: A_SIGNED == B_SIGNED from here\r
+`ifdef DSP_SIGNEDONLY\r
+       else if (!A_SIGNED) begin\r
+               wire [1:0] _;\r
+               \$mul #(\r
+                       .A_SIGNED(1),\r
+                       .B_SIGNED(1),\r
+                       .A_WIDTH(A_WIDTH + 1),\r
+                       .B_WIDTH(B_WIDTH + 1),\r
+                       .Y_WIDTH(Y_WIDTH + 2)\r
+               ) _TECHMAP_REPLACE_ (\r
+                       .A({1'b0, A}),\r
+                       .B({1'b0, B}),\r
+                       .Y({_, Y})\r
+               );\r
+       end\r
+`endif\r
        else if (A_WIDTH < B_WIDTH)\r
                \$mul #(\r
                        .A_SIGNED(B_SIGNED),\r