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mn10300.c (mn10300_match_ccmode): Fix where we look for cc setter after the compare...
authorJeff Law <law@redhat.com>
Sat, 13 May 2017 14:40:53 +0000 (08:40 -0600)
committerJeff Law <law@gcc.gnu.org>
Sat, 13 May 2017 14:40:53 +0000 (08:40 -0600)
2017-05-12  Jeff Law  <law@redhat.com>
    Jakub Jelinek  <jakub@redhat.com>

* config/mn10300/mn10300.c (mn10300_match_ccmode): Fix where
we look for cc setter after the compare-elim changes.
* config/mn10300/mn10300.md (addsi3_flags): Fix order of patterns
within the vector to match what compare-elim now expects.
(subsi3_flags, andsi3_flags, iorsi3_flags): Likewise.
(xorsi3_flags, one_cmplsi2_flags): Likewise.

* config/rx/rx.c (rx_match_ccmode): Fix where we look cc setter
after the compare-elim changes.
* config/rx/rx.md (abssi2_flags): Fix order of patterns within
the vector to match what compare-elim now expects.
(addsi3_flags, adc_flags, addsi3_flags peepholes): Likewise.
(andsi3_flags, negsi2_flags, one_cmplsi2_flags): Likewise.
(iorsi3_flags, rotlsi3_flags, rotrsi3_flags): Likewise.
(ashrsi3_flags, lshrsi3_flags, ashlsi3_flags): Likewise.
(ssaddsi3, subsi3_flags, sbb_flags, xorsi3_flags): Likewise.

* config/visium/visium.c (single_set_and_flags): Fix where
we look for cc setter after the compare-elim changes.
* config/visium/visium.md (flags_subst_logic): Fix order of patterns
with the vector to match what compare-elim now expects.
(flags_subst_arith, add<mode>3_insn_set_carry): Likewise.
(add<mode>3_insn_set_overflow, addsi3_insn_set_carry): Likewise.
(addsi3_insn_set_overflow, sub<mode>3_insn_set_carry): Likewise.
(sub<mode>3_insn_set_overflow, subsi3_insn_set_carry): Likewise.
(subsi3_insn_set_overflow, negsi2_insn_set_carry): Likewise.
(neg<mode>2_insn_set_overflow): Likewise.

Co-Authored-By: Jakub Jelinek <jakub@redhat.com>
From-SVN: r248007

gcc/ChangeLog patch | blob | history
gcc/config/mn10300/mn10300.c patch | blob | history
gcc/config/mn10300/mn10300.md patch | blob | history
gcc/config/rx/rx.c patch | blob | history
gcc/config/rx/rx.md patch | blob | history
gcc/config/visium/visium.c patch | blob | history
gcc/config/visium/visium.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b58aacf9b53845a38fb40c76b042d62b0fb199ff..b144a538bef82478d6210d3a6eca331aee857c91 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,34 @@
+2017-05-12  Jeff Law  <law@redhat.com>
+           Jakub Jelinek  <jakub@redhat.com>
+
+       * config/mn10300/mn10300.c (mn10300_match_ccmode): Fix where    
+       we look for cc setter after the compare-elim changes.
+       * config/mn10300/mn10300.md (addsi3_flags): Fix order of patterns
+       within the vector to match what compare-elim now expects.
+       (subsi3_flags, andsi3_flags, iorsi3_flags): Likewise.
+       (xorsi3_flags, one_cmplsi2_flags): Likewise.
+
+       * config/rx/rx.c (rx_match_ccmode): Fix where we look cc setter
+       after the compare-elim changes.
+       * config/rx/rx.md (abssi2_flags): Fix order of patterns within
+       the vector to match what compare-elim now expects.
+       (addsi3_flags, adc_flags, addsi3_flags peepholes): Likewise.
+       (andsi3_flags, negsi2_flags, one_cmplsi2_flags): Likewise.
+       (iorsi3_flags, rotlsi3_flags, rotrsi3_flags): Likewise.
+       (ashrsi3_flags, lshrsi3_flags, ashlsi3_flags): Likewise.
+       (ssaddsi3, subsi3_flags, sbb_flags, xorsi3_flags): Likewise.
+
+       * config/visium/visium.c (single_set_and_flags): Fix where
+       we look for cc setter after the compare-elim changes.
+       * config/visium/visium.md (flags_subst_logic): Fix order of patterns
+       with the vector to match what compare-elim now expects.
+       (flags_subst_arith, add<mode>3_insn_set_carry): Likewise.
+       (add<mode>3_insn_set_overflow, addsi3_insn_set_carry): Likewise.
+       (addsi3_insn_set_overflow, sub<mode>3_insn_set_carry): Likewise.
+       (sub<mode>3_insn_set_overflow, subsi3_insn_set_carry): Likewise.
+       (subsi3_insn_set_overflow, negsi2_insn_set_carry): Likewise.
+       (neg<mode>2_insn_set_overflow): Likewise.
+
 2017-05-12  Jim Wilson  <jim.wilson@linaro.org>
 
        PR middle-end/79794
diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c
index dae04d31fa6c9171cad9e73f0da1119ec3705ade..301207fa66a333983ca556e32ae36f9ac2fb0f17 100644 (file)
--- a/gcc/config/mn10300/mn10300.c
+++ b/gcc/config/mn10300/mn10300.c
@@ -2895,7 +2895,7 @@ mn10300_match_ccmode (rtx insn, machine_mode cc_mode)
 
   gcc_checking_assert (XVECLEN (PATTERN (insn), 0) == 2);
 
-  op1 = XVECEXP (PATTERN (insn), 0, 1);
+  op1 = XVECEXP (PATTERN (insn), 0, 0);
   gcc_checking_assert (GET_CODE (SET_SRC (op1)) == COMPARE);
 
   flags = SET_DEST (op1);
diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md
index 5a77aab2d537dad471f26c9ce8fb87898c6f93af..b4bd2795687b413cc4d8cb65e53a42555d632469 100644 (file)
--- a/gcc/config/mn10300/mn10300.md
+++ b/gcc/config/mn10300/mn10300.md
@@ -592,12 +592,12 @@
 
 ;; Note that ADD IMM,SP does not set the flags, so omit that here.
 (define_insn "*addsi3_flags"
-  [(set (match_operand:SI          0 "register_operand"  "=r,!r")
-       (plus:SI (match_operand:SI 1 "register_operand"  "%0, r")
-                (match_operand:SI 2 "nonmemory_operand" "ri, r")))
-   (set (reg CC_REG)
-       (compare (plus:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (plus:SI (match_operand:SI 1 "register_operand"  "%0, r")
+                         (match_operand:SI 2 "nonmemory_operand" "ri, r"))
+                (const_int 0)))
+   (set (match_operand:SI          0 "register_operand"  "=r,!r")
+       (plus:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)"
   { return mn10300_output_add (operands, true); }
   [(set_attr "timings" "11,22")]
@@ -605,12 +605,12 @@
 
 ;; A helper to expand the above, with the CC_MODE filled in.
 (define_expand "addsi3_flags"
-  [(parallel [(set (match_operand:SI 0 "register_operand")
-                  (plus:SI (match_operand:SI 1 "register_operand")
-                           (match_operand:SI 2 "nonmemory_operand")))
-             (set (reg:CCZNC CC_REG)
+  [(parallel [(set (reg:CCZNC CC_REG)
                   (compare:CCZNC (plus:SI (match_dup 1) (match_dup 2))
-                                 (const_int 0)))])]
+                                 (const_int 0)))
+             (set (match_operand:SI 0 "register_operand")
+                  (plus:SI (match_operand:SI 1 "register_operand")
+                           (match_operand:SI 2 "nonmemory_operand")))])]
   ""
 )
 
@@ -791,12 +791,12 @@
 )
 
 (define_insn "*subsi3_flags"
-  [(set (match_operand:SI           0 "register_operand"  "=r, r")
-       (minus:SI (match_operand:SI 1 "register_operand"   "0, r")
-                 (match_operand:SI 2 "nonmemory_operand"  "ri,r")))
-   (set (reg CC_REG)
-       (compare (minus:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (minus:SI (match_operand:SI 1 "register_operand"  "0, r")
+                          (match_operand:SI 2 "nonmemory_operand" "ri,r"))
+                (const_int 0)))
+   (set (match_operand:SI           0 "register_operand"  "=r, r")
+       (minus:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)"
   "@
    sub %2,%0
@@ -807,12 +807,12 @@
 
 ;; A helper to expand the above, with the CC_MODE filled in.
 (define_expand "subsi3_flags"
-  [(parallel [(set (match_operand:SI 0 "register_operand")
-                  (minus:SI (match_operand:SI 1 "register_operand")
-                            (match_operand:SI 2 "nonmemory_operand")))
-             (set (reg:CCZNC CC_REG)
+  [(parallel [(set (reg:CCZNC CC_REG)
                   (compare:CCZNC (minus:SI (match_dup 1) (match_dup 2))
-                                 (const_int 0)))])]
+                                 (const_int 0)))
+             (set (match_operand:SI 0 "register_operand")
+                  (minus:SI (match_operand:SI 1 "register_operand")
+                            (match_operand:SI 2 "nonmemory_operand")))])]
   ""
 )
 
@@ -1195,12 +1195,12 @@
 )
 
 (define_insn "*andsi3_flags"
-  [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
-       (and:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
-               (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
-   (set (reg CC_REG)
-       (compare (and:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (and:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
+                        (match_operand:SI 2 "nonmemory_operand" " i,D,r"))
+                (const_int 0)))
+   (set (match_operand:SI         0 "register_operand"  "=D,D,r")
+       (and:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
   "@
    and %2,%0
@@ -1282,12 +1282,12 @@
 )
 
 (define_insn "*iorsi3_flags"
-  [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
-       (ior:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
-               (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
-   (set (reg CC_REG)
-       (compare (ior:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (ior:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
+                        (match_operand:SI 2 "nonmemory_operand" " i,D,r"))
+                (const_int 0)))
+   (set (match_operand:SI         0 "register_operand"  "=D,D,r")
+       (ior:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
   "@
    or %2,%0
@@ -1318,12 +1318,12 @@
 )
 
 (define_insn "*xorsi3_flags"
-  [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
-       (xor:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
-               (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
-   (set (reg CC_REG)
-       (compare (xor:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (xor:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
+                        (match_operand:SI 2 "nonmemory_operand" " i,D,r"))
+                (const_int 0)))
+   (set (match_operand:SI         0 "register_operand"  "=D,D,r")
+       (xor:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
   "@
    xor %2,%0
@@ -1346,11 +1346,11 @@
 )
 
 (define_insn "*one_cmplsi2_flags"
-  [(set (match_operand:SI         0 "register_operand" "=D")
-       (not:SI (match_operand:SI 1 "register_operand" " 0")))
-   (set (reg CC_REG)
-       (compare (not:SI (match_dup 1))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
+                (const_int 0)))
+   (set (match_operand:SI         0 "register_operand" "=D")
+       (not:SI (match_dup 1)))]
   "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
   "not %0"
 )
diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c
index 1e74f380bdb284c2ca664e711dc2359874f4dff5..9d512b8959bbeef92b2e7cd39873f41f5249a367 100644 (file)
--- a/gcc/config/rx/rx.c
+++ b/gcc/config/rx/rx.c
@@ -3205,7 +3205,7 @@ rx_match_ccmode (rtx insn, machine_mode cc_mode)
 
   gcc_checking_assert (XVECLEN (PATTERN (insn), 0) == 2);
 
-  op1 = XVECEXP (PATTERN (insn), 0, 1);
+  op1 = XVECEXP (PATTERN (insn), 0, 0);
   gcc_checking_assert (GET_CODE (SET_SRC (op1)) == COMPARE);
 
   flags = SET_DEST (op1);
diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md
index eae3e3b7d492beacb44f07ce57ac206c9ab86e3c..bd74fe88b747eb1d155e29d0432bd19118a46538 100644 (file)
--- a/gcc/config/rx/rx.md
+++ b/gcc/config/rx/rx.md
@@ -843,11 +843,11 @@
 )
 
 (define_insn "*abssi2_flags"
-  [(set (match_operand:SI         0 "register_operand" "=r,r")
-        (abs:SI (match_operand:SI 1 "register_operand"  "0,r")))
-   (set (reg CC_REG)
-       (compare (abs:SI (match_dup 1))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+        (compare (abs:SI (match_operand:SI 1 "register_operand"  "0,r"))
+                (const_int 0)))
+   (set (match_operand:SI                 0 "register_operand" "=r,r")
+       (abs:SI (match_dup 1)))]
   ;; Note - although the ABS instruction does set the O bit in the processor
   ;; status word, it does not do so in a way that is comparable with the CMP
   ;; instruction.  Hence we use CC_ZSmode rather than CC_ZSOmode.
@@ -897,12 +897,12 @@
 )
 
 (define_insn "*addsi3_flags"
-  [(set (match_operand:SI          0 "register_operand"  "=r,r,r,r,r,r,r,r,r,r,r,r,r,r")
-       (plus:SI (match_operand:SI 1 "register_operand"  "%0,0,0,0,0,0,0,r,r,r,r,r,r,0")
-                (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q")))
-   (set (reg CC_REG)
-       (compare (plus:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (plus:SI (match_operand:SI 1 "register_operand"  "%0,0,0,0,0,0,0,r,r,r,r,r,r,0")
+                         (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q"))
+                (const_int 0)))
+   (set (match_operand:SI                  0 "register_operand"  "=r,r,r,r,r,r,r,r,r,r,r,r,r,r")
+       (plus:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
   "@
   add\t%2, %0
@@ -925,12 +925,13 @@
 
 ;; A helper to expand the above with the CC_MODE filled in.
 (define_expand "addsi3_flags"
-  [(parallel [(set (match_operand:SI 0 "register_operand")
-                  (plus:SI (match_operand:SI 1 "register_operand")
-                           (match_operand:SI 2 "rx_source_operand")))
-             (set (reg:CC_ZSC CC_REG)
-                  (compare:CC_ZSC (plus:SI (match_dup 1) (match_dup 2))
-                                  (const_int 0)))])]
+  [(parallel [(set (reg:CC_ZSC CC_REG)
+                  (compare:CC_ZSC
+                    (plus:SI (match_operand:SI 1 "register_operand")
+                             (match_operand:SI 2 "rx_source_operand"))
+                    (const_int 0)))
+             (set (match_operand:SI 0 "register_operand")
+                  (plus:SI (match_dup 1) (match_dup 2)))])]
 )
 
 (define_insn "adc_internal"
@@ -948,20 +949,20 @@
 )
 
 (define_insn "*adc_flags"
-  [(set (match_operand:SI     0 "register_operand"  "=r,r,r,r,r,r")
-       (plus:SI
-         (plus:SI
-           (ltu:SI (reg:CC CC_REG) (const_int 0))
-           (match_operand:SI 1 "register_operand"  "%0,0,0,0,0,0"))
-         (match_operand:SI   2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q")))
-   (set (reg CC_REG)
-       (compare 
+  [(set (reg CC_REG)
+       (compare
          (plus:SI
            (plus:SI
              (ltu:SI (reg:CC CC_REG) (const_int 0))
-             (match_dup 1))
-           (match_dup 2))
-         (const_int 0)))]
+             (match_operand:SI 1 "register_operand"  "%0,0,0,0,0,0"))
+           (match_operand:SI   2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q"))
+         (const_int 0)))
+   (set (match_operand:SI      0 "register_operand"  "=r,r,r,r,r,r")
+       (plus:SI
+         (plus:SI
+           (ltu:SI (reg:CC CC_REG) (const_int 0))
+           (match_dup 1))
+         (match_dup 2)))]
   "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
   "adc\t%2, %0"
   [(set_attr "timings" "11,11,11,11,11,33")
@@ -980,11 +981,11 @@
         (compare:CC (match_dup 0)
                     (const_int 0)))]
   ""
-  [(parallel [(set (match_dup 0)
-                  (plus:SI (match_dup 1) (const_int 0)))
-             (set (reg:CC_ZSC CC_REG)
+  [(parallel [(set (reg:CC_ZSC CC_REG)
                   (compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0))
-                                  (const_int 0)))])]
+                                  (const_int 0)))
+             (set (match_dup 0)
+                  (plus:SI (match_dup 1) (const_int 0))) ])]
 )
 
 (define_peephole2
@@ -994,11 +995,11 @@
         (compare:CC (match_dup 1)
                     (const_int 0)))]
   ""
-  [(parallel [(set (match_dup 0)
-                  (plus:SI (match_dup 1) (const_int 0)))
-             (set (reg:CC_ZSC CC_REG)
+  [(parallel [(set (reg:CC_ZSC CC_REG)
                   (compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0))
-                                  (const_int 0)))])]
+                                  (const_int 0)))
+             (set (match_dup 0)
+                  (plus:SI (match_dup 1) (const_int 0)))])]
 )
 
 (define_expand "adddi3"
@@ -1109,12 +1110,12 @@
 )
 
 (define_insn "*andsi3_flags"
-  [(set (match_operand:SI         0 "register_operand"  "=r,r,r,r,r,r,r,r,r")
-       (and:SI (match_operand:SI 1 "register_operand"  "%0,0,0,0,0,0,r,r,0")
-               (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
-   (set (reg CC_REG)
-       (compare (and:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (and:SI (match_operand:SI 1 "register_operand"  "%0,0,0,0,0,0,r,r,0")
+                        (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))
+                (const_int 0)))
+   (set (match_operand:SI                 0 "register_operand"  "=r,r,r,r,r,r,r,r,r")
+       (and:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
   "@
   and\t%2, %0
@@ -1341,11 +1342,11 @@
 ;; Note that the O and C flags are not set as per a normal compare,
 ;; and thus are unusable in that context.
 (define_insn "*negsi2_flags"
-  [(set (match_operand:SI         0 "register_operand" "=r,r")
-        (neg:SI (match_operand:SI 1 "register_operand"  "0,r")))
-   (set (reg CC_REG)
-       (compare (neg:SI (match_dup 1))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+        (compare (neg:SI (match_operand:SI 1 "register_operand"  "0,r"))
+                (const_int 0)))
+   (set (match_operand:SI                 0 "register_operand" "=r,r")
+       (neg:SI (match_dup 1)))]
   "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
   "@
   neg\t%0
@@ -1365,11 +1366,11 @@
 )
 
 (define_insn "*one_cmplsi2_flags"
-  [(set (match_operand:SI         0 "register_operand" "=r,r")
-       (not:SI (match_operand:SI 1 "register_operand"  "0,r")))
-   (set (reg CC_REG)
-       (compare (not:SI (match_dup 1))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (not:SI (match_operand:SI 1 "register_operand"  "0,r"))
+                (const_int 0)))
+   (set (match_operand:SI                 0 "register_operand" "=r,r")
+       (not:SI (match_dup 1)))]
   "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
   "@
   not\t%0
@@ -1398,12 +1399,12 @@
 )
 
 (define_insn "*iorsi3_flags"
-  [(set (match_operand:SI         0 "register_operand" "=r,r,r,r,r,r,r,r,r")
-       (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
-               (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
-   (set (reg CC_REG)
-       (compare (ior:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
+                        (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))
+                (const_int 0)))
+   (set (match_operand:SI                 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
+       (ior:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
   "@
   or\t%2, %0
@@ -1430,12 +1431,12 @@
 )
 
 (define_insn "*rotlsi3_flags"
-  [(set (match_operand:SI            0 "register_operand" "=r")
-       (rotate:SI (match_operand:SI 1 "register_operand"  "0")
-                  (match_operand:SI 2 "rx_shift_operand" "rn")))
-   (set (reg CC_REG)
-       (compare (rotate:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (rotate:SI (match_operand:SI 1 "register_operand"  "0")
+                           (match_operand:SI 2 "rx_shift_operand" "rn"))
+                (const_int 0)))
+   (set (match_operand:SI                    0 "register_operand" "=r")
+       (rotate:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
   "rotl\t%2, %0"
   [(set_attr "length" "3")]
@@ -1452,12 +1453,12 @@
 )
 
 (define_insn "*rotrsi3_flags"
-  [(set (match_operand:SI              0 "register_operand" "=r")
-       (rotatert:SI (match_operand:SI 1 "register_operand"  "0")
-                    (match_operand:SI 2 "rx_shift_operand" "rn")))
-   (set (reg CC_REG)
-       (compare (rotatert:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (rotatert:SI (match_operand:SI 1 "register_operand"  "0")
+                             (match_operand:SI 2 "rx_shift_operand" "rn"))
+                (const_int 0)))
+   (set (match_operand:SI                      0 "register_operand" "=r")
+       (rotatert:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
   "rotr\t%2, %0"
   [(set_attr "length" "3")]
@@ -1477,12 +1478,12 @@
 )
 
 (define_insn "*ashrsi3_flags"
-  [(set (match_operand:SI              0 "register_operand" "=r,r,r")
-       (ashiftrt:SI (match_operand:SI 1 "register_operand"  "0,0,r")
-                    (match_operand:SI 2 "rx_shift_operand"  "r,n,n")))
-   (set (reg CC_REG)
-       (compare (ashiftrt:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (ashiftrt:SI (match_operand:SI 1 "register_operand"  "0,0,r")
+                             (match_operand:SI 2 "rx_shift_operand"  "r,n,n"))
+                (const_int 0)))
+   (set (match_operand:SI              0 "register_operand" "=r,r,r")
+       (ashiftrt:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
   "@
   shar\t%2, %0
@@ -1505,12 +1506,12 @@
 )
 
 (define_insn "*lshrsi3_flags"
-  [(set (match_operand:SI              0 "register_operand" "=r,r,r")
-       (lshiftrt:SI (match_operand:SI 1 "register_operand"  "0,0,r")
-                    (match_operand:SI 2 "rx_shift_operand"  "r,n,n")))
-   (set (reg CC_REG)
-       (compare (lshiftrt:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (lshiftrt:SI (match_operand:SI 1 "register_operand"  "0,0,r")
+                             (match_operand:SI 2 "rx_shift_operand"  "r,n,n"))
+                (const_int 0)))
+   (set (match_operand:SI                      0 "register_operand" "=r,r,r")
+       (lshiftrt:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
   "@
   shlr\t%2, %0
@@ -1533,12 +1534,12 @@
 )
 
 (define_insn "*ashlsi3_flags"
-  [(set (match_operand:SI            0 "register_operand" "=r,r,r")
-       (ashift:SI (match_operand:SI 1 "register_operand"  "0,0,r")
-                  (match_operand:SI 2 "rx_shift_operand"  "r,n,n")))
-   (set (reg CC_REG)
-       (compare (ashift:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (ashift:SI (match_operand:SI 1 "register_operand"  "0,0,r")
+                           (match_operand:SI 2 "rx_shift_operand"  "r,n,n"))
+                (const_int 0)))
+   (set (match_operand:SI                    0 "register_operand" "=r,r,r")
+       (ashift:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
   "@
   shll\t%2, %0
@@ -1556,12 +1557,12 @@
   ""
   "#"
   "reload_completed"
-  [(parallel [(set (match_dup 0)
-                  (plus:SI (match_dup 1) (match_dup 2)))
-             (set (reg:CC_ZSC CC_REG)
+  [(parallel [(set (reg:CC_ZSC CC_REG)
                   (compare:CC_ZSC
                     (plus:SI (match_dup 1) (match_dup 2))
-                    (const_int 0)))])
+                    (const_int 0)))
+             (set (match_dup 0)
+                  (plus:SI (match_dup 1) (match_dup 2)))])
    (set (match_dup 0)
        (unspec:SI [(match_dup 0) (reg:CC CC_REG)] 
                   UNSPEC_BUILTIN_SAT))]
@@ -1597,12 +1598,12 @@
 ;; Note that the O flag is set as if (compare op1 op2) not for
 ;; what is described here, (compare op0 0).
 (define_insn "*subsi3_flags"
-  [(set (match_operand:SI           0 "register_operand" "=r,r,r,r,r")
-       (minus:SI (match_operand:SI 1 "register_operand"  "0,0,0,r,0")
-                 (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q")))
-   (set (reg CC_REG)
-       (compare (minus:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (minus:SI (match_operand:SI 1 "register_operand"  "0,0,0,r,0")
+                          (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q"))
+                (const_int 0)))
+   (set (match_operand:SI                   0 "register_operand" "=r,r,r,r,r")
+       (minus:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
   "@
   sub\t%2, %0
@@ -1616,12 +1617,13 @@
 
 ;; A helper to expand the above with the CC_MODE filled in.
 (define_expand "subsi3_flags"
-  [(parallel [(set (match_operand:SI 0 "register_operand")
-                  (minus:SI (match_operand:SI 1 "register_operand")
-                            (match_operand:SI 2 "rx_source_operand")))
-             (set (reg:CC_ZSC CC_REG)
-                  (compare:CC_ZSC (minus:SI (match_dup 1) (match_dup 2))
-                                  (const_int 0)))])]
+  [(parallel [(set (reg:CC_ZSC CC_REG)
+                  (compare:CC_ZSC
+                    (minus:SI (match_operand:SI 1 "register_operand")
+                              (match_operand:SI 2 "rx_source_operand"))
+                    (const_int 0)))
+             (set (match_operand:SI 0 "register_operand")
+                  (minus:SI (match_dup 1) (match_dup 2)))])]
 )
 
 (define_insn "sbb_internal"
@@ -1639,18 +1641,18 @@
 )
 
 (define_insn "*sbb_flags"
-  [(set (match_operand:SI     0 "register_operand"   "=r,r")
-       (minus:SI
-         (minus:SI
-           (match_operand:SI 1 "register_operand"   " 0,0")
-           (match_operand:SI 2 "rx_compare_operand" " r,Q"))
-         (geu:SI (reg:CC CC_REG) (const_int 0))))
-   (set (reg CC_REG)
+  [(set (reg CC_REG)
        (compare
          (minus:SI
-           (minus:SI (match_dup 1) (match_dup 2))
+           (minus:SI
+             (match_operand:SI 1 "register_operand"   " 0,0")
+             (match_operand:SI 2 "rx_compare_operand" " r,Q"))
            (geu:SI (reg:CC CC_REG) (const_int 0)))
-         (const_int 0)))]
+         (const_int 0)))
+   (set (match_operand:SI      0 "register_operand"   "=r,r")
+       (minus:SI
+         (minus:SI (match_dup 1) (match_dup 2))
+         (geu:SI (reg:CC CC_REG) (const_int 0))))]
   "reload_completed"
   "sbb\t%2, %0"
   [(set_attr "timings" "11,33")
@@ -1710,13 +1712,13 @@
 )
 
 (define_insn "*xorsi3_flags"
-  [(set (match_operand:SI         0 "register_operand" "=r,r,r,r,r,r")
-       (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
-               (match_operand:SI 2 "rx_source_operand"
-                                 "r,Sint08,Sint16,Sint24,i,Q")))
-   (set (reg CC_REG)
-       (compare (xor:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
+                        (match_operand:SI 2 "rx_source_operand"
+                                               "r,Sint08,Sint16,Sint24,i,Q"))
+                (const_int 0)))
+   (set (match_operand:SI                 0 "register_operand" "=r,r,r,r,r,r")
+       (xor:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
   "xor\t%Q2, %0"
   [(set_attr "timings" "11,11,11,11,11,33")
diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c
index b802797097afd33d3d1dc45f9fe4d8c4c56c731c..e4cdac198e1c813e550b1ac8d25a10c6c6791a99 100644 (file)
--- a/gcc/config/visium/visium.c
+++ b/gcc/config/visium/visium.c
@@ -932,10 +932,10 @@ single_set_and_flags (rtx_insn *insn)
     {
       rtx pat = PATTERN (insn);
       if (XVECLEN (pat, 0) == 2
-         && GET_CODE (XVECEXP (pat, 0, 1)) == SET
-         && REG_P (SET_DEST (XVECEXP (pat, 0, 1)))
-         && REGNO (SET_DEST (XVECEXP (pat, 0, 1))) == FLAGS_REGNUM)
-       return XVECEXP (pat, 0, 0);
+         && GET_CODE (XVECEXP (pat, 0, 0)) == SET
+         && REG_P (SET_DEST (XVECEXP (pat, 0, 0)))
+         && REGNO (SET_DEST (XVECEXP (pat, 0, 0))) == FLAGS_REGNUM)
+       return XVECEXP (pat, 0, 1);
     }
 
   return single_set (insn);
diff --git a/gcc/config/visium/visium.md b/gcc/config/visium/visium.md
index 501e874603c8e9d8779ffa65f4d020c2ce8a01d0..a1f97a252d131f7f327e3a7c80d270c532689fb1 100644 (file)
--- a/gcc/config/visium/visium.md
+++ b/gcc/config/visium/visium.md
@@ -251,9 +251,9 @@
   [(set (match_operand 0 "") (match_operand 1 ""))
    (clobber (reg:CC R_FLAGS))]
   ""
-  [(set (match_dup 0) (match_dup 1))
-   (set (reg:CC R_FLAGS)
-       (compare:CC (match_dup 1) (const_int 0)))])
+  [(set (reg:CC R_FLAGS)
+       (compare:CC (match_dup 1) (const_int 0)))
+   (set (match_dup 0) (match_dup 1))])
 
 (define_subst_attr "subst_logic" "flags_subst_logic" "_flags" "_set_flags")
 
@@ -261,9 +261,9 @@
   [(set (match_operand 0 "") (match_operand 1 ""))
    (clobber (reg:CC R_FLAGS))]
   ""
-  [(set (match_dup 0) (match_dup 1))
-   (set (reg:CCNZ R_FLAGS)
-       (compare:CCNZ (match_dup 1) (const_int 0)))])
+  [(set (reg:CCNZ R_FLAGS)
+       (compare:CCNZ (match_dup 1) (const_int 0)))
+   (set (match_dup 0) (match_dup 1))])
 
 (define_subst_attr "subst_arith" "flags_subst_arith" "_flags" "_set_flags")
 
@@ -794,23 +794,23 @@
   [(set_attr "type" "arith")])
 
 (define_insn "*add<mode>3_insn_set_carry"
-  [(set (match_operand:QHI 0 "register_operand" "=r")
-       (plus:QHI (match_operand:QHI 1 "register_operand" "%r")
-                 (match_operand:QHI 2 "register_operand" "r")))
-   (set (reg:CCC R_FLAGS)
-       (compare:CCC (plus:QHI (match_dup 1) (match_dup 2))
-                    (match_dup 1)))]
+  [(set (reg:CCC R_FLAGS)
+       (compare:CCC (plus:QHI (match_operand:QHI 1 "register_operand" "%r")
+                              (match_operand:QHI 2 "register_operand" "r"))
+                    (match_dup 1)))
+   (set (match_operand:QHI 0 "register_operand" "=r")
+       (plus:QHI (match_dup 1) (match_dup 2)))]
   "reload_completed"
   "add<s>   %0,%1,%2"
   [(set_attr "type" "arith")])
 
 (define_insn "*add<mode>3_insn_set_overflow"
-  [(set (match_operand:QHI 0 "register_operand" "=r")
-       (plus:QHI (match_operand:QHI 1 "register_operand" "%r")
-                 (match_operand:QHI 2 "register_operand" "r")))
-   (set (reg:CCV R_FLAGS)
-       (compare:CCV (plus:QHI (match_dup 1) (match_dup 2))
-                    (unspec:QHI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV)))]
+  [(set (reg:CCV R_FLAGS)
+       (compare:CCV (plus:QHI (match_operand:QHI 1 "register_operand" "%r")
+                              (match_operand:QHI 2 "register_operand" "r"))
+                    (unspec:QHI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV)))
+   (set (match_operand:QHI 0 "register_operand" "=r")
+       (plus:QHI (match_dup 1) (match_dup 2)))]
   "reload_completed"
   "add<s>   %0,%1,%2"
   [(set_attr "type" "arith")])
@@ -858,12 +858,12 @@
   [(set_attr "type" "arith")])
 
 (define_insn "addsi3_insn_set_carry"
-  [(set (match_operand:SI 0 "register_operand"          "=r,r")
-       (plus:SI (match_operand:SI 1 "register_operand" "%r,0")
-                (match_operand:SI 2 "real_add_operand" " r,J")))
-   (set (reg:CCC R_FLAGS)
-       (compare:CCC (plus:SI (match_dup 1) (match_dup 2))
-                    (match_dup 1)))]
+  [(set (reg:CCC R_FLAGS)
+       (compare:CCC (plus:SI (match_operand:SI 1 "register_operand" "%r,0")
+                             (match_operand:SI 2 "real_add_operand" " r,J"))
+                    (match_dup 1)))
+   (set (match_operand:SI 0 "register_operand"          "=r,r")
+       (plus:SI (match_dup 1) (match_dup 2)))]
   "reload_completed"
   "@
     add.l   %0,%1,%2
@@ -871,12 +871,12 @@
   [(set_attr "type" "arith")])
 
 (define_insn "*addsi3_insn_set_overflow"
-  [(set (match_operand:SI 0 "register_operand"          "=r,r")
-       (plus:SI (match_operand:SI 1 "register_operand" "%r,0")
-                (match_operand:SI 2 "real_add_operand" " r,J")))
-   (set (reg:CCV R_FLAGS)
-       (compare:CCV (plus:SI (match_dup 1) (match_dup 2))
-                    (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV)))]
+  [(set (reg:CCV R_FLAGS)
+       (compare:CCV (plus:SI (match_operand:SI 1 "register_operand" "%r,0")
+                             (match_operand:SI 2 "real_add_operand" " r,J"))
+                    (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV)))
+   (set (match_operand:SI 0 "register_operand"          "=r,r")
+       (plus:SI (match_dup 1) (match_dup 2)))]
   "reload_completed"
   "@
     add.l   %0,%1,%2
@@ -1009,22 +1009,22 @@
   [(set_attr "type" "arith")])
 
 (define_insn "*sub<mode>3_insn_set_carry"
-  [(set (match_operand:QHI 0 "register_operand" "=r")
-       (minus:QHI (match_operand:QHI 1 "reg_or_0_operand" "rO")
-                  (match_operand:QHI 2 "register_operand" "r")))
-   (set (reg:CC R_FLAGS)
-       (compare:CC (match_dup 1) (match_dup 2)))]
+  [(set (reg:CC R_FLAGS)
+       (compare:CC (match_operand:QHI 1 "reg_or_0_operand" "r0")
+                   (match_operand:QHI 2 "register_operand" "r")))
+   (set (match_operand:QHI 0 "register_operand" "=r")
+       (minus:QHI (match_dup 1) (match_dup 2)))]
   "reload_completed"
   "sub<s>   %0,%r1,%2"
   [(set_attr "type" "arith")])
 
 (define_insn "*sub<mode>3_insn_set_overflow"
-  [(set (match_operand:QHI 0 "register_operand" "=r")
-       (minus:QHI (match_operand:QHI 1 "reg_or_0_operand" "rO")
-                  (match_operand:QHI 2 "register_operand" "r")))
-   (set (reg:CCV R_FLAGS)
-       (compare:CCV (minus:QHI (match_dup 1) (match_dup 2))
-                    (unspec:QHI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV)))]
+  [(set (reg:CCV R_FLAGS)
+       (compare:CCV (minus:QHI (match_operand:QHI 1 "reg_or_0_operand" "r0")
+                               (match_operand:QHI 2 "register_operand" "r"))
+                    (unspec:QHI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV)))
+   (set (match_operand:QHI 0 "register_operand" "=r")
+       (minus:QHI (match_dup 1) (match_dup 2)))]
   "reload_completed"
   "sub<s>   %0,%r1,%2"
   [(set_attr "type" "arith")])
@@ -1072,11 +1072,11 @@
   [(set_attr "type" "arith")])
 
 (define_insn "subsi3_insn_set_carry"
-  [(set (match_operand:SI 0 "register_operand"           "=r,r")
-       (minus:SI (match_operand:SI 1 "register_operand" " r,0")
-                 (match_operand:SI 2 "real_add_operand" " r,J")))
-   (set (reg:CC R_FLAGS)
-       (compare:CC (match_dup 1) (match_dup 2)))]
+  [(set (reg:CC R_FLAGS)
+       (compare:CC (match_operand:SI 1 "register_operand" "r,0")
+                   (match_operand:SI 2 "real_add_operand" "r,J")))
+   (set (match_operand:SI 0 "register_operand"           "=r,r")
+       (minus:SI (match_dup 1) (match_dup 2)))]
   "reload_completed"
   "@
     sub.l   %0,%r1,%2
@@ -1084,12 +1084,12 @@
   [(set_attr "type" "arith")])
 
 (define_insn "*subsi3_insn_set_overflow"
-  [(set (match_operand:SI 0 "register_operand"           "=r,r")
-       (minus:SI (match_operand:SI 1 "register_operand" " r,0")
-                 (match_operand:SI 2 "real_add_operand" " r,J")))
-   (set (reg:CCV R_FLAGS)
-       (compare:CCV (minus:SI (match_dup 1) (match_dup 2))
-                    (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV)))]
+  [(set (reg:CCV R_FLAGS)
+       (compare:CCV (minus:SI (match_operand:SI 1 "register_operand" "r,0")
+                              (match_operand:SI 2 "real_add_operand" "r,J"))
+                    (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV)))
+   (set (match_operand:SI 0 "register_operand"           "=r,r")
+       (minus:SI (match_dup 1) (match_dup 2)))]
   "reload_completed"
   "@
     sub.l   %0,%1,%2
@@ -1209,20 +1209,21 @@
   [(set_attr "type" "arith")])
 
 (define_insn "negsi2_insn_set_carry"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (neg:SI (match_operand:SI 1 "register_operand" "r")))
-   (set (reg:CCC R_FLAGS)
-       (compare:CCC (not:SI (match_dup 1)) (const_int -1)))]
+  [(set (reg:CCC R_FLAGS)
+       (compare:CCC (not:SI (match_operand:SI 1 "register_operand" "r"))
+                    (const_int -1)))
+   (set (match_operand:SI 0 "register_operand" "=r")
+        (neg:SI (match_dup 1)))]
   "reload_completed"
   "sub.l   %0,r0,%1"
   [(set_attr "type" "arith")])
 
 (define_insn "*neg<mode>2_insn_set_overflow"
-  [(set (match_operand:I 0 "register_operand" "=r")
-       (neg:I (match_operand:I 1 "register_operand" "r")))
-   (set (reg:CCV R_FLAGS)
-       (compare:CCV (neg:I (match_dup 1))
-                    (unspec:I [(match_dup 1)] UNSPEC_NEGV)))]
+  [(set (reg:CCV R_FLAGS)
+       (compare:CCV (neg:I (match_operand:I 1 "register_operand" "r"))
+                    (unspec:I [(match_dup 1)] UNSPEC_NEGV)))
+   (set (match_operand:I 0 "register_operand" "=r")
+       (neg:I (match_dup 1)))]
   "reload_completed"
   "sub<s>   %0,r0,%1"
   [(set_attr "type" "arith")])