log memory in a more fancy format, like hexdump -C

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 58d2dc3f532fb4dedfe0a928608c814df5877c96..ef528fddfd6feb40091931c90f941f680f0d4e9a 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -660,6 +660,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
 
         # "raw" memory
         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
+        self.mem.log_fancy(kind=LogKind.InstrInOuts)
         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
         # MMU mode, redirect underlying Mem through RADIX
         if mmu:

diff --git a/src/openpower/decoder/isa/mem.py b/src/openpower/decoder/isa/mem.py
index c41e436e5e5133a6bebaf76b9df81d4d60baa51c..6e2226272635c95f4ea6f00b219e2dc3c5530e3b 100644 (file)
--- a/src/openpower/decoder/isa/mem.py
+++ b/src/openpower/decoder/isa/mem.py
@@ -12,14 +12,10 @@ related bugs:
 * https://bugs.libre-soc.org/show_bug.cgi?id=424
 """
 
-from copy import copy
-from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
-                                        selectconcat)
-
-from openpower.decoder.helpers import exts, gtu, ltu, undefined
-from openpower.util import log
+from collections import defaultdict
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.util import log, LogKind
 import math
-import sys
 
 
 def swap_order(x, nbytes):
@@ -155,3 +151,46 @@ class Mem:
                 continue
             print ("%016x: %016x" % ((k*8) & 0xffffffffffffffff, self.mem[k]))
         return res
+
+    def log_fancy(self, *, kind=LogKind.Default, name="Memory",
+                  log2_line_size=4, log2_column_chunk_size=3):
+        line_size = 1 << log2_line_size
+        subline_mask = line_size - 1
+        column_chunk_size = 1 << log2_column_chunk_size
+
+        def make_line():
+            return bytearray(line_size)
+        mem_lines = defaultdict(make_line)
+        subword_range = range(1 << self.word_log2)
+        for k in self.mem.keys():
+            addr = k << self.word_log2
+            for _ in subword_range:
+                v = self.ld(addr, width=1)
+                mem_lines[addr >> log2_line_size][addr & subline_mask] = v
+                addr += 1
+
+        lines = []
+        last_line_index = None
+        for line_index in sorted(mem_lines.keys()):
+            line_addr = line_index << log2_line_size
+            if last_line_index is not None \
+                    and last_line_index + 1 != line_index:
+                lines.append("*")
+            last_line_index = line_index
+            line_bytes = mem_lines[line_index]
+            line_str = f"0x{line_addr:08X}:"
+            for col_chunk in range(0, line_size,
+                                   column_chunk_size):
+                line_str += " "
+                for i in range(column_chunk_size):
+                    line_str += f" {line_bytes[col_chunk + i]:02X}"
+            line_str += "  |"
+            for i in range(line_size):
+                if 0x20 <= line_bytes[i] <= 0x7E:
+                    line_str += chr(line_bytes[i])
+                else:
+                    line_str += "."
+            line_str += "|"
+            lines.append(line_str)
+        lines = "\n".join(lines)
+        log(f"\n{name}:\n{lines}\n", kind=kind)

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index 5282c1e69f46430b1a41bd464b5a5597fbd0b8c6..a831027cf59a276033e6014b410b30622e5ae624 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -254,7 +254,7 @@ class TestRunnerBase(FHDLTestCase):
                         kind=LogKind.InstrInOuts)
                     log("sprs", test.sprs, kind=LogKind.InstrInOuts)
                     log("cr", test.cr, kind=LogKind.InstrInOuts)
-                    log("mem", test.mem, kind=LogKind.InstrInOuts)
+                    log("mem", test.mem)
                     log("msr", test.msr, kind=LogKind.InstrInOuts)
 
                     def format_assembly(assembly):