flatten: simplify.

Flattening does not benefit from topologically sorting cells within
a module when processing them.

diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc
index f37be685b16cd3021410c03eb888e41f52f8f6e0..82e6974952f455b3265e7d0e636f6f9df7109c61 100644 (file)
--- a/passes/techmap/flatten.cc
+++ b/passes/techmap/flatten.cc
@@ -260,10 +260,6 @@ struct FlattenWorker
 
                SigMap sigmap(module);
 
-               TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
-               dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_to_inbit;
-               dict<RTLIL::SigBit, pool<RTLIL::Cell*>> outbit_to_cell;
-
                for (auto cell : module->selected_cells())
                {
                        if (!design->has(cell->type))
@@ -279,37 +275,6 @@ struct FlattenWorker
                                continue;
                        }
 
-                       for (auto &conn : cell->connections())
-                       {
-                               RTLIL::SigSpec sig = sigmap(conn.second);
-                               sig.remove_const();
-
-                               if (GetSize(sig) == 0)
-                                       continue;
-
-                               RTLIL::Module *tpl = design->module(cell->type);
-                               RTLIL::Wire *port = tpl->wire(conn.first);
-                               if (port && port->port_input)
-                                       cell_to_inbit[cell].insert(sig.begin(), sig.end());
-                               if (port && port->port_output)
-                                       for (auto &bit : sig)
-                                               outbit_to_cell[bit].insert(cell);
-                       }
-
-                       cells.node(cell);
-               }
-
-               for (auto &it_right : cell_to_inbit)
-               for (auto &it_sigbit : it_right.second)
-               for (auto &it_left : outbit_to_cell[it_sigbit])
-                       cells.edge(it_left, it_right.first);
-
-               cells.sort();
-
-               for (auto cell : cells.sorted)
-               {
-                       log_assert(cell == module->cell(cell->name));
-
                        RTLIL::Module *tpl = design->module(cell->type);
                        dict<IdString, RTLIL::Const> parameters(cell->parameters);