add larger PLL reset countdown to give ULX3S a chance to stabilise

diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index 8bff5bb6fa5362cc78480a543e151b929ae7848e..14ffabe870b2ebf64bac81f5c4778a056081b113 100644 (file)
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -9,6 +9,7 @@ entity toplevel is
        MEMORY_SIZE   : positive := (384*1024);
        RAM_INIT_FILE : string   := "firmware.hex";
        RESET_LOW     : boolean  := true;
+       PLL_RESET_BITS     : positive  := 18;
        CLK_INPUT     : positive := 100000000;
        CLK_FREQUENCY : positive := 100000000;
         HAS_FPU       : boolean  := true;
@@ -41,7 +42,8 @@ begin
 
     reset_controller: entity work.soc_reset
        generic map(
-           RESET_LOW => RESET_LOW
+           RESET_LOW => RESET_LOW,
+           PLL_RESET_BITS => PLL_RESET_BITS
            )
        port map(
            ext_clk => ext_clk,