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whoops error in accessing icache.ibus which is an intermediary
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 18 Dec 2021 01:08:11 +0000 (01:08 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 18 Dec 2021 01:08:11 +0000 (01:08 +0000)
set of signals

src/openpower/test/runner.py patch | blob | history

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index cc91b75ddeda2604335343e9054e38b882474844..333bb11739717f79083833cbf1f9ca05b54041dd 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -483,7 +483,7 @@ class TestRunnerBase(FHDLTestCase):
             default_mem = self.rom
             sim.add_sync_process(wrap(wb_get(dcache.bus,
                                              default_mem, "DCACHE")))
-            sim.add_sync_process(wrap(wb_get(icache.ibus,
+            sim.add_sync_process(wrap(wb_get(icache.bus,
                                              default_mem, "ICACHE")))
 
         with sim.write_vcd("issuer_simulator.vcd"):