Made servicing_atomic a counter and added started writes:

a function for setting the flag to indicate that
the rmw_writes started issuing

diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 329730ffd6766bae0f35bc403cd9ebbbe80b478e..7da3d317a1168e2d9fb90cb1972f59d393a97cdc 100644 (file)
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -22,6 +22,7 @@ public:
   virtual const string getName() const = 0;   // return instance name
   virtual const MachineType getMachineType() const = 0;
   virtual void set_atomic(Address addr) = 0;
+  virtual void started_writes() = 0;
   virtual void clear_atomic() = 0;
 
   virtual void print(ostream & out) const = 0;

diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index eb3430b7f44ba343be672eab87dd5f0130e92a9b..780c1128e5267ab2c05c9a29a0c39afd558d2bb0 100644 (file)
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -416,6 +416,9 @@ int64_t Sequencer::makeRequest(const RubyRequest & request)
           m_dataCache_ptr->clearLocked(line_address(Address(request.paddr)));
         }
       }
+      if (request.type == RubyRequestType_RMW_Write) {
+        m_controller->started_writes();
+      }
       issueRequest(request);
 
     // TODO: issue hardware prefetches here

diff --git a/src/mem/slicc/symbols/StateMachine.cc b/src/mem/slicc/symbols/StateMachine.cc
index 46047ec25c8671cd91a98abf3f3d64e6f6ffab46..0a3d4a85debb0f77417994d75f74cad054ca7303 100644 (file)
--- a/src/mem/slicc/symbols/StateMachine.cc
+++ b/src/mem/slicc/symbols/StateMachine.cc
@@ -291,6 +291,7 @@ void StateMachine::printControllerH(ostream& out, string component)
   out << "  void printConfig(ostream& out) const;" << endl;
   out << "  void wakeup();" << endl;
   out << "  void set_atomic(Address addr);" << endl;
+  out << "  void started_writes();" << endl;
   out << "  void clear_atomic();" << endl;
   out << "  void printStats(ostream& out) const { s_profiler.dumpStats(out); }" << endl;
   out << "  void clearStats() { s_profiler.clearStats(); }" << endl;
@@ -301,7 +302,7 @@ void StateMachine::printControllerH(ostream& out, string component)
     out << "  int m_" << m_config_parameters->ref(i)->getName() << ";" << endl;
   }
   if (strncmp(component.c_str(), "L1Cache", 7) == 0) {
-    out << "  bool servicing_atomic;" << endl;
+    out << "  int servicing_atomic;" << endl;
     out << "  bool started_receiving_writes;" << endl;
     out << "  Address locked_read_request1;" << endl;
     out << "  Address locked_read_request2;" << endl;
@@ -416,7 +417,7 @@ void StateMachine::printControllerC(ostream& out, string component)
   out << " : m_name(name)" << endl;
   out << "{ " << endl;
   if (strncmp(component.c_str(), "L1Cache", 7) == 0) {
-    out << "  servicing_atomic = false;" << endl;
+    out << "  servicing_atomic = 0;" << endl;
     out << "  started_receiving_writes = false;" << endl;
     out << "  locked_read_request1 = Address(-1);" << endl;
     out << "  locked_read_request2 = Address(-1);" << endl;
@@ -728,23 +729,6 @@ void StateMachine::printControllerC(ostream& out, string component)
 
       string c_code_string = action.lookupPair("c_code");
 
-      // add here:
-      if (0/*strncmp(component.c_str(), "L1Cache", 7) == 0*/) {
-        if (c_code_string.find("writeCallback") != string::npos) {
-          string::size_type pos = c_code_string.find("(((*m_L1Cache_sequencer_ptr)).writeCallback");
-          assert(pos != string::npos);
-          string atomics_string = "\n  if (servicing_atomic) { \n \
-   servicing_atomic = false; \n \
-   locked_read_request = Address(-1); \n \
- } \n \
- else if (!servicing_atomic) { \n \
-   if (addr == locked_read_request) { \n \
-     servicing_atomic = true; \n \
-   } \n \
- } \n  ";
-          c_code_string.insert(pos, atomics_string);
-        }
-      }
       out << c_code_string;
 
       out << "}" << endl;
@@ -811,10 +795,11 @@ void StateMachine::printCWakeup(ostream& out, string component)
     assert(pos != string::npos);
     string atomics_string = "\n \
              if ((((*in_msg_ptr)).m_Type) == CacheRequestType_ATOMIC) { \n \
-               if (!servicing_atomic) { \n \
+               if (servicing_atomic == 0) { \n \
                   if (locked_read_request1 == Address(-1)) { \n \
                     assert(read_counter == 0); \n \ 
                     locked_read_request1 = addr;  \n \
+                    assert(read_counter == 0); \n \
                     read_counter++; \n \
                   } \n \
                   else if (addr == locked_read_request1) { \n \
@@ -824,48 +809,61 @@ void StateMachine::printCWakeup(ostream& out, string component)
                     assert(0); // should never be here if servicing one request at a time \n\ 
                   } \n \
                } \n \
-               else if (addr != locked_read_request1) { \n \
-                 if (!started_receiving_writes) { \n \
+               else if (!started_receiving_writes) { \n \
+               if (servicing_atomic == 1) { \n \
                   if (locked_read_request2 == Address(-1)) { \n \
+                    assert(locked_read_request1 != Address(-1)); \n \
+                    assert(read_counter == 1); \n \ 
+                    locked_read_request2 = addr;  \n \
                     assert(read_counter == 1); \n \
-                    locked_read_request2 = addr; \n \
                     read_counter++; \n \
                   } \n \
-                  else if (locked_read_request3 == Address(-1)) { \n \
+                  else if (addr == locked_read_request2) { \n \
+                    ; // do nothing \n\ 
+                  } \n \
+                  else { \n \
+                    assert(0); // should never be here if servicing one request at a time \n\ 
+                  } \n \
+               } \n \
+               else if (servicing_atomic == 2) { \n \
+                  if (locked_read_request3 == Address(-1)) { \n \
+                    assert(locked_read_request1 != Address(-1)); \n \
+                    assert(locked_read_request2 != Address(-1)); \n \
+                    assert(read_counter == 1); \n \ 
+                    locked_read_request3 = addr;  \n \
                     assert(read_counter == 2); \n \
-                    locked_read_request3 = addr; \n \
                     read_counter++; \n \
                   } \n \
-                  else if (locked_read_request4 == Address(-1)) { \n \
+                  else if (addr == locked_read_request3) { \n \
+                    ; // do nothing \n\ 
+                  } \n \
+                  else { \n \
+                    assert(0); // should never be here if servicing one request at a time \n\ 
+                  } \n \
+               } \n \
+               else if (servicing_atomic == 3) { \n \
+                  if (locked_read_request4 == Address(-1)) { \n \
+                    assert(locked_read_request1 != Address(-1)); \n \
+                    assert(locked_read_request2 != Address(-1)); \n \
+                    assert(locked_read_request3 != Address(-1)); \n \
+                    assert(read_counter == 1); \n \ 
+                    locked_read_request4 = addr;  \n \
                     assert(read_counter == 3); \n \
-                    locked_read_request4 = addr; \n \
-                    read_counter++; \n \
+                    read_counter++; \n \ 
+                  } \n \
+                  else if (addr == locked_read_request4) { \n \
+                    ; // do nothing \n\ 
                   } \n \
                   else { \n \
-                    // reached limit of addresses that could be locked \n \
-                    // this can happen if there are multiple optimized consequtive shifts \n \
-                    assert(0); \n \
+                    assert(0); // should never be here if servicing one request at a time \n\ 
                   } \n \
-                 } \n \
                } \n \
-             } \n \
-             else { \n \
-               // if an atomic is followed by non-atomic, reset -> shift optimization \n \
-               // remove this and assert(0) once shifts are resolved \n \
-               if (locked_read_request1 != Address(-1)) { \n \
-                 locked_read_request1 = Address(-1); \n \
-                 locked_read_request2 = Address(-1); \n \
-                 locked_read_request3 = Address(-1); \n \
-                 locked_read_request4 = Address(-1); \n \
-                 servicing_atomic = false; \n \
-                 started_receiving_writes = false; \n \
-                 read_counter = 0; \n \
+               else { \n \
+                 assert(0); \n \
                } \n \
              } \n \
+             } \n \  
                ";
-
-
-
     output.insert(pos, atomics_string);
     /*string foo = "// Cannot do anything with this transition, go check next doable transition (mostly likely of next port)\n";
     string::size_type next_pos = output.find(foo, pos);
@@ -888,12 +886,16 @@ void StateMachine::printCWakeup(ostream& out, string component)
           out << "    if ((((*m_L1Cache_forwardToCache_ptr)).isReady())) {" << endl;
           out << "      const RequestMsg* in_msg_ptr;" << endl;
           out << "      in_msg_ptr = dynamic_cast<const RequestMsg*>(((*m_L1Cache_forwardToCache_ptr)).peek());" << endl;
-          out << "      if ((servicing_atomic && (locked_read_request1 == ((*in_msg_ptr)).m_Address) || " << endl;
-          out << "      (locked_read_request2 == ((*in_msg_ptr)).m_Address) || (locked_read_request3 == ((*in_msg_ptr)).m_Address) || " << endl;
-          out << "      (locked_read_request4 == ((*in_msg_ptr)).m_Address))) { " << endl;
+          out << "      if ((((servicing_atomic == 1)  && (locked_read_request1 == ((*in_msg_ptr)).m_Address)) || " << endl;
+          out << "       ((servicing_atomic == 2)  && (locked_read_request1 == ((*in_msg_ptr)).m_Address || locked_read_request2 == ((*in_msg_ptr)).m_Address)) || " << endl;
+          out << "       ((servicing_atomic == 3)  && (locked_read_request1 == ((*in_msg_ptr)).m_Address || locked_read_request2 == ((*in_msg_ptr)).m_Address || locked_read_request3 == ((*in_msg_ptr)).m_Address)) || " << endl;
+          out << "       ((servicing_atomic == 4)  && (locked_read_request1 == ((*in_msg_ptr)).m_Address || locked_read_request2 == ((*in_msg_ptr)).m_Address || locked_read_request3 == ((*in_msg_ptr)).m_Address || locked_read_request1 == ((*in_msg_ptr)).m_Address)))) {" << endl;
+//          out << "      (locked_read_request2 == ((*in_msg_ptr)).m_Address) || (locked_read_request3 == ((*in_msg_ptr)).m_Address) || " << endl;
+//          out << "      (locked_read_request4 == ((*in_msg_ptr)).m_Address))) { " << endl;
 
           out << "        postpone = true;" << endl;
           out << "      }" << endl;
+              
           out << "    }" << endl;
           out << "    if (!postpone) {" << endl;
         }
@@ -924,18 +926,19 @@ void StateMachine::printCWakeup(ostream& out, string component)
   if (strncmp(component.c_str(), "L1Cache", 7) == 0) {
     out << "void " << component << "_Controller::set_atomic(Address addr)" << endl;
     out << "{" << endl;
-    out << "  if (!servicing_atomic) { " << endl;
-    out << "    assert(addr == locked_read_request1); " << endl; 
-    out << "    servicing_atomic = true; " << endl;
-    out << "  }" << endl;
+    out << "  servicing_atomic++; " << endl;
     out << "}" << endl;
-    out << "void " << component << "_Controller::clear_atomic()" << endl;
+    out << "void " << component << "_Controller::started_writes()" << endl;
     out << "{" << endl;
-    out << "  assert(servicing_atomic); " << endl;
     out << "  started_receiving_writes = true; " << endl;
+    out << "}" << endl;
+    out << "void " << component << "_Controller::clear_atomic()" << endl;
+    out << "{" << endl;
+    out << "  assert(servicing_atomic > 0); " << endl;
     out << "  read_counter--; " << endl;
+    out << "  servicing_atomic--; " << endl;
     out << "  if (read_counter == 0) { " << endl;
-    out << "    servicing_atomic = false; " << endl;
+    out << "    servicing_atomic = 0; " << endl;
     out << "    started_receiving_writes = false; " << endl;
     out << "    locked_read_request1 = Address(-1); " << endl;
     out << "    locked_read_request2 = Address(-1); " << endl;
@@ -945,6 +948,10 @@ void StateMachine::printCWakeup(ostream& out, string component)
     out << "}" << endl;
   }
   else {
+    out << "void " << component << "_Controller::started_writes()" << endl;
+    out << "{" << endl;
+    out << "  assert(0); " << endl;
+    out << "}" << endl;
     out << "void " << component << "_Controller::set_atomic(Address addr)" << endl;
     out << "{" << endl;
     out << "  assert(0); " << endl;