add (sigh) to the hack-job get_pdecode_idx_out2() in ISACaller

really should be relying on PowerDecoder2 but hey

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index a3ccd7e4fff177e69cf9db7ad2d8868097815ff8..60a4c1f4f8c19aff568fb8072de0e01bf6cbcae5 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -514,10 +514,14 @@ def get_pdecode_idx_out2(dec2, name):
                 out, o_isvec)
             if upd == LDSTMode.update.value:
                 return out, o_isvec
+    if name == 'RS':
+        fft_en = yield dec2.implicit_rs
+        if fft_en:
+            log("get_pdecode_idx_out2", out_sel, OutSel.RS.value,
+                out, o_isvec)
+            return out, o_isvec
     if name == 'FRS':
-        int_op = yield dec2.dec.op.internal_op
         fft_en = yield dec2.implicit_rs
-        # if int_op == MicrOp.OP_FP_MADD.value and fft_en:
         if fft_en:
             log("get_pdecode_idx_out2", out_sel, OutSel.FRS.value,
                 out, o_isvec)

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 14a376d96cfa033d3f9bf92fca9cdbe003db9f8a..dfa6f8f60a9f91a8603e0f5c412fdd690b042e57 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -514,7 +514,7 @@ class DecodeOut2(Elaboratable):
         # will be offset by VL in hardware
         # with m.Case(MicrOp.OP_FP_MADD):
         with m.If(self.implicit_rs):
-            comb += self.reg_out.data.eq(self.dec.FRT)
+            comb += self.reg_out.data.eq(self.dec.FRT) # same as RT, for pcdec
             comb += self.reg_out.ok.eq(1)
             comb += self.rs_en.eq(1)
 

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index f2b47f2f42ddb4cfb065045179d03de4bea47f93..0f040fa61c7a71a0444bdd7bf6ce37e53a64a538 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -751,6 +751,7 @@ class OutSel(Enum):
     RT_OR_ZERO = 4
     FRT = 5
     FRS = 6
+    RS = 7
 
 
 @unique