spelling corrections

diff --git a/updates/018_2019may27_nlnet_grant_approved.mdwn b/updates/018_2019may27_nlnet_grant_approved.mdwn
index 9e35bbd86957e9a5493dd45cce2e625360e492bb..6c07056eed1ff78037a7960a7e409f524ea13de5 100644 (file)
--- a/updates/018_2019may27_nlnet_grant_approved.mdwn
+++ b/updates/018_2019may27_nlnet_grant_approved.mdwn
@@ -75,7 +75,7 @@ Adder and Multiplier Unit.  Given that we are doing a Vector Processing
 front-end onto SIMD back-end operations, it makes sense to save gates by
 allowing the ADD and MUL units to be able to optionally handle a batch
 of 8-bit operations, or half the number of 16-bit operations, or a quarter
-of the number of 32-bit operations or one eigth of the number of64-bit
+of the number of 32-bit operations or one eighth of the number of 64-bit
 operations.  In this way, a lot less gates are required than if they
 were separate units.  The unit tests demonstrate that the code that Jacob
 has written provide RISC-V mul, mulh, mulhu and mulhsu functionality.