class USBBlaster(GenericProgrammer):
needs_bitreverse = False
+ def __init__(self, cable_name="USB-Blaster", device_id=1):
+ self.cable_name = cable_name
+ self.device_id = device_id
+
def load_bitstream(self, bitstream_file, cable_suffix=""):
subprocess.call(["quartus_pgm", "-m", "jtag", "-c",
- "USB-Blaster{}".format(cable_suffix), "-o",
- "p;{}".format(bitstream_file)])
+ "{}{}".format(self.cable_name, cable_suffix), "-o",
+ "p;{}@{}".format(bitstream_file, self.device_id)])
quartus_fit --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}
quartus_asm --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}
quartus_sta {build_name} -c {build_name}
-quartus_cpf -c {build_name}.sof {build_name}.rbf
+if [ -f "{build_name}.sof" ]
+then
+ quartus_cpf -c {build_name}.sof {build_name}.rbf
+fi
""".format(build_name=build_name) # noqa
build_script_file = "build_" + build_name + ".sh"
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v"
v_output.write(v_file)
- sources = platform.sources + [(v_file, "verilog", "work")]
+ sources = platform.sources | {(v_file, "verilog", "work")}
_build_files(platform.device,
sources,
platform.verilog_include_paths,
-import os
+import os, sys
+from litex.build import tools
class GenericProgrammer:
def __init__(self, flash_proxy_basename=None):
self.flash_proxy_basename = flash_proxy_basename
self.flash_proxy_dirs = [
+ "~/.migen", "/usr/local/share/migen", "/usr/share/migen",
+ "~/.mlabs", "/usr/local/share/mlabs", "/usr/share/mlabs",
"~/.litex", "/usr/local/share/litex", "/usr/share/litex"]
def set_flash_proxy_dir(self, flash_proxy_dir):
def find_flash_proxy(self):
for d in self.flash_proxy_dirs:
fulldir = os.path.abspath(os.path.expanduser(d))
- fullname = os.path.join(fulldir, self.flash_proxy_basename)
+ fullname = tools.cygpath(os.path.join(fulldir, self.flash_proxy_basename))
if os.path.exists(fullname):
return fullname
raise OSError("Failed to find flash proxy bitstream")
special_overrides = common.lattice_ecpx_special_overrides
def build(self, platform, fragment, build_dir="build", build_name="top",
- toolchain_path="/opt/Diamond", run=True):
+ toolchain_path="/opt/Diamond", run=True, **kwargs):
os.makedirs(build_dir, exist_ok=True)
cwd = os.getcwd()
os.chdir(build_dir)
fragment = fragment.get_fragment()
platform.finalize(fragment)
- v_output = platform.get_verilog(fragment)
+ v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v"
v_output.write(v_file)
-# This file is Copyright (c) 2017 William D. Jones <thor0505@comcast.net>
+# This file is Copyright (c) 2016-2017 William D. Jones <thor0505@comcast.net>
# License: BSD
import os
icetime_pkg_opts, freq_constraint):
if sys.platform in ("win32", "cygwin"):
script_ext = ".bat"
- build_script_contents = "@echo off\nrem Autogenerated by Migen\n"
+ build_script_contents = "@echo off\nrem Autogenerated by Migen\n\n"
fail_stmt = " || exit /b"
else:
script_ext = ".sh"
- build_script_contents = "# Autogenerated by Migen\nset -e\n"
+ build_script_contents = "# Autogenerated by Migen\nset -e\n\n"
fail_stmt = ""
for s in build_template:
# platform.device should be of the form "ice40-{lp384, hx1k, etc}-{tq144, etc}"
def build(self, platform, fragment, build_dir="build", build_name="top",
- toolchain_path=None, use_nextpnr=True, run=True):
+ use_nextpnr=True, run=True, **kwargs):
os.makedirs(build_dir, exist_ok=True)
cwd = os.getcwd()
os.chdir(build_dir)
fragment = fragment.get_fragment()
platform.finalize(fragment)
- v_output = platform.get_verilog(fragment)
+ v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v"
v_output.write(v_file)
return series_size_str[2:]
def gen_read_files(self, platform, main):
- sources = platform.sources + [(main, "verilog", "work")]
+ sources = platform.sources | {(main, "verilog", "work")}
incflags = ""
read_files = list()
for path in platform.verilog_include_paths:
def __init__(self, xcf_template):
self.xcf_template = xcf_template
- def load_bitstream(self, bitstream_file, toolchain_path=''):
+ def load_bitstream(self, bitstream_file):
xcf_file = bitstream_file.replace(".bit", ".xcf")
xcf_content = self.xcf_template.format(bitstream_file=bitstream_file)
tools.write_to_file(xcf_file, xcf_content)
- if toolchain_path:
- pgrcmd = os.path.join(toolchain_path, 'bin/lin64/pgrcmd')
- else:
- pgrcmr = 'pgrcmr'
- subprocess.call([pgrcmd, "-infile", xcf_file])
+ subprocess.call(["pgrcmd", "-infile", xcf_file])
class IceStormProgrammer(GenericProgrammer):
# Ditto with user data.
subprocess.call(["tinyprog", "-u", bitstream_file])
else:
- # Provide override so user can program wherever they wish (outside
- # of bootloader region).
- subprocess.call(["tinyprog", "-a", str(address), "--program-image",
+ # Provide override so user can program wherever they wish.
+ subprocess.call(["tinyprog", "-a", str(address), "-p",
bitstream_file])
# Force user image to boot if a user reset tinyfpga, the bootloader
# is active, and the user image need not be reprogrammed.
def boot(self):
subprocess.call(["tinyprog", "-b"])
+
+
+class MyStormProgrammer(GenericProgrammer):
+ def __init__(self, serial_port):
+ self.serial_port = serial_port
+
+ def load_bitstream(self, bitstream_file):
+ import serial
+ with serial.Serial(self.serial_port) as port:
+ with open(bitstream_file, "rb") as f:
+ port.write(f.read())
def _format_lpf(signame, pin, others, resname):
fmt_c = [_format_constraint(c) for c in ([Pins(pin)] + others)]
r = ""
- print(fmt_c)
for pre, suf in fmt_c:
r += pre + "\"" + signame + "\"" + suf + ";\n"
return r
self.freq_constraints = dict()
def build(self, platform, fragment, build_dir="build", build_name="top",
- toolchain_path=None, run=True):
+ toolchain_path=None, run=True, **kwargs):
if toolchain_path is None:
toolchain_path = "/usr/share/trellis/"
os.makedirs(build_dir, exist_ok=True)
fragment = fragment.get_fragment()
platform.finalize(fragment)
- top_output = platform.get_verilog(fragment, name=build_name)
+ top_output = platform.get_verilog(fragment, name=build_name, **kwargs)
named_sc, named_pc = platform.resolve_signals(top_output.ns)
top_file = build_name + ".v"
top_output.write(top_file)
import re
import subprocess
import sys
+import ctypes
def language_by_filename(name):
for line in stdout:
print(sub_rules(line, rules, max_matches), end="")
return proc.wait()
+
+
+if sys.platform == "cygwin":
+ cygwin1 = ctypes.CDLL("/usr/bin/cygwin1.dll")
+ cygwin_conv_path_proto = ctypes.CFUNCTYPE(
+ ctypes.c_ssize_t, # Return
+ ctypes.c_uint, # what
+ ctypes.c_void_p, # from
+ ctypes.c_void_p, # to
+ ctypes.c_size_t) # size
+ cygwin_conv_path = cygwin_conv_path_proto(("cygwin_conv_path", cygwin1),
+ ((1, "what"),
+ (1, "from"),
+ (1, "to"),
+ (1, "size")))
+
+
+ def cygpath_to_windows(path):
+ what = ctypes.c_uint(0) # CCP_POSIX_TO_WIN_A
+ fro = ctypes.c_char_p(path.encode('utf-8'))
+ to = ctypes.byref(ctypes.create_string_buffer(260))
+ size = ctypes.c_size_t(260)
+
+ cygwin_conv_path(what, fro, to, size)
+ return ctypes.cast(to, ctypes.c_char_p).value.decode('utf-8')
+
+ # Convert cygwin paths to Windows native paths. This is a noop otherwise.
+ def cygpath(p):
+ return cygpath_to_windows(p)
+else:
+ def cygpath(p):
+ return p
from litex.build.xilinx.platform import XilinxPlatform
-from litex.build.xilinx.programmer import XC3SProg, FpgaProg, VivadoProgrammer, iMPACT
+from litex.build.xilinx.programmer import UrJTAG, XC3SProg, FpgaProg, VivadoProgrammer, iMPACT, Adept
def _build_xst_files(device, sources, vincpaths, build_name, xst_opt):
prj_contents = ""
for filename, language, library in sources:
- prj_contents += language + " " + library + " " + filename + "\n"
+ prj_contents += language + " " + library + " " + tools.cygpath(filename) + "\n"
tools.write_to_file(build_name + ".prj", prj_contents)
xst_contents = """run
-p {device}
""".format(build_name=build_name, xst_opt=xst_opt, device=device)
for path in vincpaths:
- xst_contents += "-vlgincdir " + path + "\n"
+ xst_contents += "-vlgincdir " + tools.cygpath(path) + "\n"
tools.write_to_file(build_name + ".xst", xst_contents)
fail_stmt = ""
if source:
settings = common.settings(ise_path, ver, "ISE_DS")
- build_script_contents += source_cmd + settings + "\n"
-
- ext = "ngc"
- build_script_contents += """
+ build_script_contents += source_cmd + tools.cygpath(settings) + "\n"
+ if mode == "edif":
+ ext = "edif"
+ else:
+ ext = "ngc"
+ build_script_contents += """
xst -ifn {build_name}.xst{fail_stmt}
"""
named_sc, named_pc = platform.resolve_signals(vns)
v_file = build_name + ".v"
v_output.write(v_file)
- sources = platform.sources + [(v_file, "verilog", "work")]
+ sources = platform.sources | {(v_file, "verilog", "work")}
if mode in ("xst", "cpld"):
_build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt)
isemode = mode
quit
""".format(data=data_file, flash_part=self.flash_part, device=device)
_run_vivado(self.vivado_path, self.vivado_ver, cmds)
+
+
+class Adept(GenericProgrammer):
+ """Using the Adept tool with an onboard Digilent "USB JTAG" cable.
+
+ You need to install Adept Utilities V2 from
+ http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2
+ """
+
+ needs_bitreverse = False
+
+ def __init__(self, board, index, flash_proxy_basename=None):
+ GenericProgrammer.__init__(self, flash_proxy_basename)
+ self.board = board
+ self.index = index
+
+ def load_bitstream(self, bitstream_file):
+ subprocess.call([
+ "djtgcfg",
+ "--verbose",
+ "prog", "-d", self.board,
+ "-i", str(self.index),
+ "-f", bitstream_file,
+ ])
+
+ def flash(self, address, data_file):
+ raise ValueError("Flashing unsupported with DigilentAdept tools")
)
def build(self, platform, fragment, build_dir="build", build_name="top",
- toolchain_path=None, source=True, run=True, synth_mode="vivado", **kwargs):
- if toolchain_path is None:
- if sys.platform == "win32":
- toolchain_path = "C:\\Xilinx\\Vivado"
- elif sys.platform == "cygwin":
- toolchain_path = "/cygdrive/c/Xilinx/Vivado"
- else:
- toolchain_path = "/opt/Xilinx/Vivado"
+ toolchain_path="/opt/Xilinx/Vivado", source=True, run=True):
os.makedirs(build_dir, exist_ok=True)
cwd = os.getcwd()
os.chdir(build_dir)
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v"
v_output.write(v_file)
- sources = platform.sources + [(v_file, "verilog", "work")]
+ sources = platform.sources | {(v_file, "verilog", "work")}
edifs = platform.edifs
ips = platform.ips
self._build_batch(platform, sources, edifs, ips, build_name, synth_mode=synth_mode)
projects / litex.git / commitdiff