Remove Xilinx test

diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys
index a717c54f1564abb02d21c46c2423db9065f1e3f6..16e5f40e161fb412e7b159881aa53a702131b8e3 100644 (file)
--- a/tests/various/shregmap.ys
+++ b/tests/various/shregmap.ys
@@ -31,37 +31,3 @@ sat -verify -prove-asserts -show-ports -seq 5 miter
 
 #design -load gate
 #stat
-
-##########
-
-design -load read
-design -copy-to model $__XILINX_SHREG_
-hierarchy -top shregmap_variable_test
-prep
-design -save gold
-
-simplemap t:$dff t:$dffe
-shregmap -tech xilinx
-
-#stat
-# show -width
-# write_verilog -noexpr -norename
-select -assert-count 1 t:$_DFF_P_
-select -assert-count 2 t:$__XILINX_SHREG_
-
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
-prep
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports -seq 5 miter
-
-# design -load gold
-# stat
-
-# design -load gate
-# stat
-