self.comb += self.mimpid.eq(Constant(0, 32))
self.comb += self.mhartid.eq(Constant(0, 32))
+class Regs:
+ def __init__(self, comb, sync):
+ self.comb = comb
+ self.sync = sync
+
+ self.ra_en = Signal(reset=1)
+ self.rb_en = Signal(reset=1)
+ self.wen = Signal(name="register_wen")
+
+ self.rs1 = Signal(32, name="register_rs1")
+ self.rs2 = Signal(32, name="register_rs2")
+ self.wval = Signal(32, name="register_wval")
+
+ self.rs_a = Signal(5, name="register_rs_a")
+ self.rs_b = Signal(5, name="register_rs_b")
+ self.rd = Signal(32, name="register_rd")
class CPU(Module):
"""
# return [m.mcause.eq(0),
# ]
- def write_register(self, register_number, value):
- return If(register_number != 0,
- self.registers[register_number].eq(value)
- )
-
def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
s = [ms.mpie.eq(ms.mie),
ms.mie.eq(0),
lui_auipc_result)
return Case(ft.output_state, c)
+ def write_register(self, rd, val):
+ return [self.regs.rd.eq(rd),
+ self.regs.wval.eq(val),
+ self.regs.wen.eq(1)
+ ]
+
def handle_valid(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
ft, dc,
load_store_misaligned,
lui_auipc_result):
# fetch action ack trap
i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
- self.handle_trap(m, mstatus, ft, dc,
- load_store_misaligned)
+ [self.handle_trap(m, mstatus, ft, dc,
+ load_store_misaligned),
+ self.regs.wen.eq(0) # no writing to registers
+ ]
)
# load
i = i.Elif((dc.act & (DA.fence | DA.fence_i |
DA.store | DA.branch)) != 0,
# do nothing
+ self.regs.wen.eq(0) # no writing to registers
)
return i
end
"""
def __init__(self):
+ Module.__init__(self)
self.clk = ClockSignal()
self.reset = ResetSignal()
self.tty_write = Signal()
reset_vector.eq(ram_start)
mtvec.eq(ram_start + 0x40)
- l = []
- for i in range(31):
- r = Signal(32, name="register%d" % i)
- l.append(r)
- self.sync += r.eq(Constant(0, 32))
- self.registers = Array(l)
+ self.regs = Regs(self.comb, self.sync)
+
+ rf = Instance("RegFile", name="regfile",
+ i_ra_en = self.regs.ra_en,
+ i_rb_en = self.regs.rb_en,
+ i_w_en = self.regs.wen,
+ o_read_a = self.regs.rs1,
+ o_read_b = self.regs.rs2,
+ i_writeval = self.regs.wval,
+ i_rs_a = self.regs.rs_a,
+ i_rs_b = self.regs.rs_b,
+ i_rd = self.regs.rd)
+
+ self.specials += rf
mi = MemoryInterface()
)
self.specials += cd
- register_rs1 = Signal(32)
- register_rs2 = Signal(32)
- self.comb += If(dc.rs1 == 0,
- register_rs1.eq(0)
- ).Else(
- register_rs1.eq(self.registers[dc.rs1-1]))
- self.comb += If(dc.rs2 == 0,
- register_rs2.eq(0)
- ).Else(
- register_rs2.eq(self.registers[dc.rs2-1]))
+ self.comb += self.regs.rs_a.eq(dc.rs1)
+ self.comb += self.regs.rs_b.eq(dc.rs2)
load_store_address = Signal(32)
load_store_address_low_2 = Signal(2)
- self.comb += load_store_address.eq(dc.immediate + register_rs1)
+ self.comb += load_store_address.eq(dc.immediate + self.regs.rs1)
self.comb += load_store_address_low_2.eq(
- dc.immediate[:2] + register_rs1[:2])
+ dc.immediate[:2] + self.regs.rs1[:2])
load_store_misaligned = Signal()
# XXX not obvious
b3 = Mux(load_store_address_low_2[1],
- Mux(load_store_address_low_2[0], register_rs2[0:8],
- register_rs2[8:16]),
- Mux(load_store_address_low_2[0], register_rs2[16:24],
- register_rs2[24:32]))
- b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
- register_rs2[16:24])
- b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
- register_rs2[8:16])
- b0 = register_rs2[0:8]
+ Mux(load_store_address_low_2[0], self.regs.rs2[0:8],
+ self.regs.rs2[8:16]),
+ Mux(load_store_address_low_2[0], self.regs.rs2[16:24],
+ self.regs.rs2[24:32]))
+ b2 = Mux(load_store_address_low_2[1], self.regs.rs2[0:8],
+ self.regs.rs2[16:24])
+ b1 = Mux(load_store_address_low_2[0], self.regs.rs2[0:8],
+ self.regs.rs2[8:16])
+ b0 = self.regs.rs2[0:8]
self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
alu_b = Signal(32)
alu_result = Signal(32)
- self.comb += alu_a.eq(register_rs1)
+ self.comb += alu_a.eq(self.regs.rs1)
self.comb += alu_b.eq(Mux(dc.opcode[5],
- register_rs2,
+ self.regs.rs2,
dc.immediate))
ali = Instance("cpu_alu", name="alu",
self.comb += ft.target_pc.eq(Cat(0,
Mux(dc.opcode != OP.jalr,
ft.output_pc[1:32],
- register_rs1[1:32] + dc.immediate[1:32])))
+ self.regs.rs1[1:32] + dc.immediate[1:32])))
misaligned_jump_target = Signal()
self.comb += misaligned_jump_target.eq(ft.target_pc[1])
branch_arg_a = Signal(32)
branch_arg_b = Signal(32)
- self.comb += branch_arg_a.eq(Cat( register_rs1[0:31],
- register_rs1[31] ^ ~dc.funct3[1]))
- self.comb += branch_arg_b.eq(Cat( register_rs2[0:31],
- register_rs2[31] ^ ~dc.funct3[1]))
+ self.comb += branch_arg_a.eq(Cat( self.regs.rs1[0:31],
+ self.regs.rs1[31] ^ ~dc.funct3[1]))
+ self.comb += branch_arg_b.eq(Cat( self.regs.rs2[0:31],
+ self.regs.rs2[31] ^ ~dc.funct3[1]))
branch_taken = Signal()
self.comb += branch_taken.eq(dc.funct3[0] ^
mip = MIP(self.comb, self.sync)
# CSR decoding
- csr = CSR(self.comb, self.sync, dc, register_rs1)
+ csr = CSR(self.comb, self.sync, dc, self.regs.rs1)
self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi,
branch_taken, misaligned_jump_target,
example.led_1,
example.led_3,
}))
-
-"""
-
- always @(posedge clk) begin:main_block
- if(reset) begin
- reset_to_initial();
- disable main_block;
- end
- case(fetch_output_state)
- `fetch_output_state_empty: begin
- end
- `fetch_output_state_trap: begin
- handle_trap();
- end
- `fetch_output_state_valid: begin:valid
- if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
- handle_trap();
- end
- else if((decode_action & `decode_action_load) != 0) begin
- if(~memory_interface_rw_wait)
- write_register(decoder_rd, loaded_value);
- end
- else if((decode_action & `decode_action_op_op_imm) != 0) begin
- write_register(decoder_rd, alu_result);
- end
- else if((decode_action & `decode_action_lui_auipc) != 0) begin
- write_register(decoder_rd, lui_auipc_result);
- end
- else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
- write_register(decoder_rd, fetch_output_pc + 4);
- end
- else if((decode_action & `decode_action_csr) != 0) begin:csr
- reg [31:0] csr_output_value;
- reg [31:0] csr_written_value;
- csr_output_value = 32'hXXXXXXXX;
- csr_written_value = 32'hXXXXXXXX;
- case(csr_number)
- `csr_cycle: begin
- csr_output_value = cycle_counter[31:0];
- end
- `csr_time: begin
- csr_output_value = time_counter[31:0];
- end
- `csr_instret: begin
- csr_output_value = instret_counter[31:0];
- end
- `csr_cycleh: begin
- csr_output_value = cycle_counter[63:32];
- end
- `csr_timeh: begin
- csr_output_value = time_counter[63:32];
- end
- `csr_instreth: begin
- csr_output_value = instret_counter[63:32];
- end
- `csr_mvendorid: begin
- csr_output_value = mvendorid;
- end
- `csr_marchid: begin
- csr_output_value = marchid;
- end
- `csr_mimpid: begin
- csr_output_value = mimpid;
- end
- `csr_mhartid: begin
- csr_output_value = mhartid;
- end
- `csr_misa: begin
- csr_output_value = misa;
- end
- `csr_mstatus: begin
- csr_output_value = make_mstatus(mstatus_tsr,
- mstatus_tw,
- mstatus_tvm,
- mstatus_mxr,
- mstatus_sum,
- mstatus_mprv,
- mstatus_xs,
- mstatus_fs,
- mstatus_mpp,
- mstatus_spp,
- mstatus_mpie,
- mstatus_spie,
- mstatus_upie,
- mstatus_mie,
- mstatus_sie,
- mstatus_uie);
- csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
- if(csr_writes) begin
- mstatus_mpie = csr_written_value[7];
- mstatus_mie = csr_written_value[3];
- end
- end
- `csr_mie: begin
- csr_output_value = 0;
- csr_output_value[11] = mie_meie;
- csr_output_value[9] = mie_seie;
- csr_output_value[8] = mie_ueie;
- csr_output_value[7] = mie_mtie;
- csr_output_value[5] = mie_stie;
- csr_output_value[4] = mie_utie;
- csr_output_value[3] = mie_msie;
- csr_output_value[1] = mie_ssie;
- csr_output_value[0] = mie_usie;
- csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
- if(csr_writes) begin
- mie_meie = csr_written_value[11];
- mie_mtie = csr_written_value[7];
- mie_msie = csr_written_value[3];
- end
- end
- `csr_mtvec: begin
- csr_output_value = mtvec;
- end
- `csr_mscratch: begin
- csr_output_value = mscratch;
- csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
- if(csr_writes)
- mscratch = csr_written_value;
- end
- `csr_mepc: begin
- csr_output_value = mepc;
- csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
- if(csr_writes)
- mepc = csr_written_value;
- end
- `csr_mcause: begin
- csr_output_value = mcause;
- csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
- if(csr_writes)
- mcause = csr_written_value;
- end
- `csr_mip: begin
- csr_output_value = 0;
- csr_output_value[11] = mip_meip;
- csr_output_value[9] = mip_seip;
- csr_output_value[8] = mip_ueip;
- csr_output_value[7] = mip_mtip;
- csr_output_value[5] = mip_stip;
- csr_output_value[4] = mip_utip;
- csr_output_value[3] = mip_msip;
- csr_output_value[1] = mip_ssip;
- csr_output_value[0] = mip_usip;
- end
- endcase
- if(csr_reads)
- write_register(decoder_rd, csr_output_value);
- end
- else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
- // do nothing
- end
- end
- endcase
- end
-
-endmodule
-"""
-
--- /dev/null
+"""
+/*
+ * Copyright 2018 Jacob Lifshay
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+`timescale 1ns / 1ps
+`include "riscv.vh"
+`include "cpu.vh"
+"""
+
+from migen import *
+from migen.fhdl import verilog
+
+class RegFile(Module):
+
+ def __init__(self):
+ Module.__init__(self)
+ l = []
+ for i in range(31):
+ r = Signal(32, name="register%d" % i)
+ l.append(r)
+ self.sync += r.eq(Constant(0, 32))
+ self.registers = Array(l)
+
+ self.ra_en = Signal() # read porta enable
+ self.rb_en = Signal() # read portb enable
+ self.w_en = Signal() # write enable
+ self.read_a = Signal(32) # result porta read
+ self.read_b = Signal(32) # result portb read
+ self.writeval = Signal(32) # value to write
+ self.rs_a = Signal(5) # register port a to read
+ self.rs_b = Signal(5) # register port b to read
+ self.rd = Signal(5) # register to write
+
+ self.sync += If(self.ra_en,
+ self.read(self.rs_a, self.read_a)
+ )
+ self.sync += If(self.rb_en,
+ self.read(self.rs_b, self.read_b)
+ )
+ self.sync += If(self.w_en,
+ self.write_register(self.rd, self.writeval)
+ )
+
+ def read(self, regnum, dest):
+ """ sets the destination register argument
+ regnum = 0, dest = 0
+ regnum != 0, dest = regs[regnum-1]
+ """
+ return If(regnum == Constant(0, 5),
+ dest.eq(Constant(0, 32))
+ ).Else(
+ dest.eq(self.registers[regnum-1])
+ )
+
+ def write_register(self, regnum, value):
+ """ writes to the register file if the regnum is not zero
+ """
+ return If(regnum != 0,
+ self.registers[regnum].eq(value)
+ )
+
+if __name__ == "__main__":
+ example = RegFile()
+ print(verilog.convert(example,
+ {
+ example.ra_en,
+ example.rb_en,
+ example.w_en,
+ example.read_a,
+ example.read_b,
+ example.writeval,
+ example.rs_a,
+ example.rs_b,
+ example.rd,
+ }))
+
projects / rv32.git / commitdiff