back.rtlil: infer bit width for instance parameters.

Otherwise, Yosys assumes it is always 32, which is often
inappropriate.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 7806ace3ed47cc195fed8936149c452c50679075..9869c61d77c15c3d78a8a094056072247612f42b 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -128,8 +128,8 @@ class _ModuleBuilder(_Namer, _BufferedBuilder, _AttrBuilder):
                 self._append("    parameter \\{} \"{}\"\n",
                              param, value.translate(self._escape_map))
             elif isinstance(value, int):
-                self._append("    parameter \\{} {:d}\n",
-                             param, value)
+                self._append("    parameter \\{} {}'{:b}\n",
+                             param, bits_for(value), value)
             elif isinstance(value, float):
                 self._append("    parameter real \\{} \"{!r}\"\n",
                              param, value)