SimInstance *top = nullptr;
std::ofstream vcdfile;
pool<IdString> clock, clockn, reset, resetn;
+ std::string timescale;
~SimWorker()
{
if (!vcdfile.is_open())
return;
+ vcdfile << stringf("$version %s $end\n", yosys_version_str);
+ vcdfile << stringf("$date ");
+ std::time_t t = std::time(nullptr);
+ vcdfile << std::put_time(std::localtime(&t), "%c %Z");
+ vcdfile << stringf(" $end\n");
+
+ if (!timescale.empty())
+ vcdfile << stringf("$timescale %s $end\n", timescale.c_str());
+
int id = 1;
top->write_vcd_header(vcdfile, id);
log(" -zinit\n");
log(" zero-initialize all uninitialized regs and memories\n");
log("\n");
+ log(" -timescale <string>\n");
+ log(" include the specified timescale declaration in the vcd\n");
+ log("\n");
log(" -n <integer>\n");
log(" number of cycles to simulate (default: 20)\n");
log("\n");
worker.resetn.insert(RTLIL::escape_id(args[++argidx]));
continue;
}
+ if (args[argidx] == "-timescale" && argidx+1 < args.size()) {
+ worker.timescale = args[++argidx];
+ continue;
+ }
if (args[argidx] == "-a") {
worker.hide_internal = false;
continue;