microcode = '''
def macroop ROL_R_I
{
- rol reg, reg, imm
+ roli reg, reg, imm
};
def macroop ROL_M_I
{
ld t1, ds, [scale, index, base], disp
- rol t1, t1, imm
+ roli t1, t1, imm
st t1, ds, [scale, index, base], disp
};
{
rdip t7
ld t1, ds, [0, t0, t7], disp
- rol t1, t1, imm
+ roli t1, t1, imm
+ st t1, ds, [0, t0, t7], disp
+};
+
+def macroop ROL_R_R
+{
+ rol reg, reg, regm
+};
+
+def macroop ROL_M_R
+{
+ ld t1, ds, [scale, index, base], disp
+ rol t1, t1, reg
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop ROL_P_R
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ rol t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
def macroop ROR_R_I
{
- ror reg, reg, imm
+ rori reg, reg, imm
};
def macroop ROR_M_I
{
ld t1, ds, [scale, index, base], disp
- ror t1, t1, imm
+ rori t1, t1, imm
st t1, ds, [scale, index, base], disp
};
{
rdip t7
ld t1, ds, [0, t0, t7], disp
- ror t1, t1, imm
+ rori t1, t1, imm
+ st t1, ds, [0, t0, t7], disp
+};
+
+def macroop ROR_R_R
+{
+ rori reg, reg, regm
+};
+
+def macroop ROR_M_R
+{
+ ld t1, ds, [scale, index, base], disp
+ rori t1, t1, reg
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop ROR_P_R
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ rori t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
def macroop RCL_R_I
{
- rcl reg, reg, imm
+ rcli reg, reg, imm
};
def macroop RCL_M_I
{
ld t1, ds, [scale, index, base], disp
- rcl t1, t1, imm
+ rcli t1, t1, imm
st t1, ds, [scale, index, base], disp
};
{
rdip t7
ld t1, ds, [0, t0, t7], disp
- rcl t1, t1, imm
+ rcli t1, t1, imm
+ st t1, ds, [0, t0, t7], disp
+};
+
+def macroop RCL_R_R
+{
+ rcli reg, reg, regm
+};
+
+def macroop RCL_M_R
+{
+ ld t1, ds, [scale, index, base], disp
+ rcli t1, t1, reg
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop RCL_P_R
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ rcli t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
def macroop RCR_R_I
{
- rcr reg, reg, imm
+ rcri reg, reg, imm
};
def macroop RCR_M_I
{
ld t1, ds, [scale, index, base], disp
- rcr t1, t1, imm
+ rcri t1, t1, imm
st t1, ds, [scale, index, base], disp
};
{
rdip t7
ld t1, ds, [0, t0, t7], disp
- rcr t1, t1, imm
+ rcri t1, t1, imm
+ st t1, ds, [0, t0, t7], disp
+};
+
+def macroop RCR_R_R
+{
+ rcri reg, reg, regm
+};
+
+def macroop RCR_M_R
+{
+ ld t1, ds, [scale, index, base], disp
+ rcri t1, t1, reg
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop RCR_P_R
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ rcri t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
'''
-#let {{
-# class RCL(Inst):
-# "GenFault ${new UnimpInstFault}"
-# class RCR(Inst):
-# "GenFault ${new UnimpInstFault}"
-#}};