/*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
#define INT_REG(name) CORE_REG(name, U64)
#define SIMD_REG(name) CORE_REG(name, U128)
+#define SYS_MPIDR_EL1 ARM64_SYS_REG(0b11, 0b000, 0b0000, 0b0000, 0b101)
+
constexpr uint64_t
kvmXReg(const int num)
{
MiscRegInfo(INT_REG(fp_regs.fpcr), MISCREG_FPCR, "FPCR"),
};
+const std::vector<ArmV8KvmCPU::MiscRegInfo> ArmV8KvmCPU::miscRegIdMap = {
+ MiscRegInfo(SYS_MPIDR_EL1, MISCREG_MPIDR_EL1, "MPIDR(EL1)"),
+};
+
ArmV8KvmCPU::ArmV8KvmCPU(ArmV8KvmCPUParams *params)
: BaseArmKvmCPU(params)
{
{
}
+void
+ArmV8KvmCPU::startup()
+{
+ BaseArmKvmCPU::startup();
+
+ // Override ID registers that KVM should "inherit" from gem5.
+ for (const auto &ri : miscRegIdMap) {
+ const uint64_t value(tc->readMiscReg(ri.idx));
+ DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
+ setOneReg(ri.kvm, value);
+ }
+}
+
void
ArmV8KvmCPU::dump() const
{
for (const auto &ri : miscRegMap)
inform(" %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm));
+ for (const auto &ri : miscRegIdMap)
+ inform(" %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm));
+
for (const auto ® : getRegList()) {
const uint64_t arch(reg & KVM_REG_ARCH_MASK);
if (arch != KVM_REG_ARM64) {
/*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
ArmV8KvmCPU(ArmV8KvmCPUParams *params);
virtual ~ArmV8KvmCPU();
+ void startup() override;
+
void dump() const override;
protected:
static const std::vector<ArmV8KvmCPU::IntRegInfo> intRegMap;
/** Mapping between gem5 misc registers registers and registers in kvm */
static const std::vector<ArmV8KvmCPU::MiscRegInfo> miscRegMap;
+ /** Mapping between gem5 ID misc registers registers and registers in kvm */
+ static const std::vector<ArmV8KvmCPU::MiscRegInfo> miscRegIdMap;
/** Cached mapping between system registers in kvm and misc regs in gem5 */
mutable std::vector<ArmV8KvmCPU::MiscRegInfo> sysRegMap;