Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 13 May 2020 19:54:06 +0000 (20:54 +0100)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Wed, 13 May 2020 19:54:30 +0000 (20:54 +0100)
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+From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date: Wed, 13 May 2020 20:54:06 +0100
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+To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
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+Subject: Re: [libre-riscv-dev] teaching the benefits of using nmigen over
+ VHDL/Verilog
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