rs6000: wm -> wa+p8v

	* config/rs6000/constraints.md (define_register_constraint "wm"):
	Delete.
	* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
	RS6000_CONSTRAINT_wm.
	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
	(rs6000_init_hard_regno_mode_ok): Adjust.
	* config/rs6000/vsx.md: Replace "wm" constraint by "wa" with "p8v".
	* doc/md.texi (Machine Constraints): Adjust.

From-SVN: r271486

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index eed982d8a74af613cd205a18d498638a07c4b989..35cb3652c9d4b9a9990c50f173cba0010997a2b8 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2019-05-21  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * config/rs6000/constraints.md (define_register_constraint "wm"):
+       Delete.
+       * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
+       RS6000_CONSTRAINT_wm.
+       * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
+       (rs6000_init_hard_regno_mode_ok): Adjust.
+       * config/rs6000/vsx.md: Replace "wm" constraint by "wa" with "p8v".
+       * doc/md.texi (Machine Constraints): Adjust.
+
 2019-05-21  Segher Boessenkool  <segher@kernel.crashing.org>
 
        * config/rs6000/constraints.md (define_register_constraint "wk"):

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 6f6062715b5df15f32667b5d86f15d1793178e5b..90a94c1d1e5e7b2bc7d5b187fa60d9d6f15d2e8b 100644 (file)
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -77,12 +77,9 @@
 (define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]"
   "Floating point register if the LFIWAX instruction is enabled or NO_REGS.")
 
-(define_register_constraint "wm" "rs6000_constraints[RS6000_CONSTRAINT_wm]"
-  "VSX register if direct move instructions are enabled, or NO_REGS.")
-
 ;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use
 ;; direct move directly, and movsf can't to move between the register sets.
-;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode
+;; There is a mode_attr that resolves to wa for SDmode and wn for SFmode
 (define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).")
 
 (define_register_constraint "wp" "rs6000_constraints[RS6000_CONSTRAINT_wp]"

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 190edb500826e94ae2a4f18ba4d981c4da4e4c8b..af8f0d2d1aaaa6184f2486a9713e9c1d529a7c6c 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2514,7 +2514,6 @@ rs6000_debug_reg_global (void)
           "wg reg_class = %s\n"
           "wi reg_class = %s\n"
           "wl reg_class = %s\n"
-          "wm reg_class = %s\n"
           "wp reg_class = %s\n"
           "wq reg_class = %s\n"
           "wr reg_class = %s\n"
@@ -2536,7 +2535,6 @@ rs6000_debug_reg_global (void)
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
-          reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
@@ -3159,7 +3157,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
        wg - Float register for power6x move insns.
        wi - FP or VSX register to hold 64-bit integers for VSX insns.
        wl - Float register if we can do 32-bit signed int loads.
-       wm - VSX register for ISA 2.07 direct move operations.
        wn - always NO_REGS.
        wr - GPR if 64-bit mode is permitted.
        ws - Register class to do ISA 2.06 DF operations.
@@ -3197,9 +3194,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
   if (TARGET_LFIWAX)
     rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS;     /* DImode  */
 
-  if (TARGET_DIRECT_MOVE)
-    rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
-
   if (TARGET_POWERPC64)
     {
       rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index cc60559f404607e8cb6801e2f7951d621ccccf4a..27055a6ddb738643297865bbb915064fa466f332 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1255,7 +1255,6 @@ enum r6000_reg_class_enum {
   RS6000_CONSTRAINT_wg,                /* FPR register for -mmfpgpr */
   RS6000_CONSTRAINT_wi,                /* FPR/VSX register to hold DImode */
   RS6000_CONSTRAINT_wl,                /* FPR register for LFIWAX */
-  RS6000_CONSTRAINT_wm,                /* VSX register for direct move */
   RS6000_CONSTRAINT_wp,                /* VSX reg for IEEE 128-bit fp TFmode. */
   RS6000_CONSTRAINT_wq,                /* VSX reg for IEEE 128-bit fp KFmode.  */
   RS6000_CONSTRAINT_wr,                /* GPR register if 64-bit  */

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index ff4ceb6268fe86556393eb66f6bf8343933acf62..6108451014b0a1039db4bb6806c482eb3293b064 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3198,10 +3198,8 @@
 
 (define_insn "vsx_extract_<mode>"
   [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=d,    d,     wr, wr")
-
        (vec_select:<VS_scalar>
-        (match_operand:VSX_D 1 "gpc_reg_operand"      "<VSa>, <VSa>, wm, wa")
-
+        (match_operand:VSX_D 1 "gpc_reg_operand"      "<VSa>, <VSa>, wa, wa")
         (parallel
          [(match_operand:QI 2 "const_0_to_1_operand"  "wD,    n,     wD, n")])))]
   "VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -3250,7 +3248,7 @@
     gcc_unreachable ();
 }
   [(set_attr "type" "veclogical,mftgpr,mftgpr,vecperm")
-   (set_attr "isa" "*,*,*,p9v")])
+   (set_attr "isa" "*,*,p8v,p9v")])
 
 ;; Optimize extracting a single scalar element from memory.
 (define_insn_and_split "*vsx_extract_<P:mode>_<VSX_D:mode>_load"

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 13a621de9768dfb16a94bc26fc5c53f139f93cb0..7ec17409bed22969a68355360e92bbfff7edf2aa 100644 (file)
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3198,7 +3198,7 @@ Any VSX register if the @option{-mvsx} option was used or NO_REGS.
 
 When using any of the register constraints (@code{wa}, @code{wd},
 @code{wf}, @code{wg}, @code{wi},
-@code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws},
+@code{wl}, @code{wp}, @code{wq}, @code{ws},
 @code{wt}, @code{wv}, or @code{ww})
 that take VSX registers, you must use @code{%x<n>} in the template so
 that the correct register is used.  Otherwise the register number
@@ -3265,9 +3265,6 @@ FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
 @item wl
 Floating point register if the LFIWAX instruction is enabled or NO_REGS.
 
-@item wm
-VSX register if direct move instructions are enabled, or NO_REGS.
-
 @item wn
 No register (NO_REGS).