ast/simplify: don't bitblast async ROMs declared as `logic`.

Fixes #2020.

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 837c14ad773e3e700e5bc10e4523c2c5505f109e..9453937e3c53128eabd917169a9ca51514fd8daf 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -3477,8 +3477,8 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
                }
        }
 
-       // also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg'
-       if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg))
+       // also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg' or 'logic'
+       if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !(is_reg || is_logic)))
                mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED;
 
        if (type == AST_MODULE && get_bool_attribute(ID::mem2reg))

diff --git a/tests/svtypes/logic_rom.sv b/tests/svtypes/logic_rom.sv
new file mode 100644 (file)
index 0000000..45fe0a4
--- /dev/null
+++ b/tests/svtypes/logic_rom.sv
@@ -0,0 +1,6 @@
+module top(input [3:0] addr, output [7:0] data);
+    logic [7:0] mem[0:15];
+    assign data = mem[addr];
+    integer i;
+    initial for(i = 0; i < 16; i = i + 1) mem[i] = i;
+endmodule

diff --git a/tests/svtypes/logic_rom.ys b/tests/svtypes/logic_rom.ys
new file mode 100644 (file)
index 0000000..7b079c1
--- /dev/null
+++ b/tests/svtypes/logic_rom.ys
@@ -0,0 +1,3 @@
+read_verilog -sv logic_rom.sv
+prep -top top
+select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=8 %i