**READ REVIEW AND INCLUDE LICENSE PERMISSION. SHORTEN CFP**
https://lists.libre-soc.org/pipermail/libre-soc-dev/2023-November/005791.html
+**ADD LINK AT TOP**
+https://fosdem.org/2024/schedule/track/libre-soc-fpga-and-vlsi/
+
This email is a Call For Participation in the
**Libre-SOC, FPGA and VLSI Devroom** at FOSDEM 2024.
+**DATES ARE OUT OF ORDER**
Devroom date: 3rd February in Brussels, Belgium
CFP deadline: **Friday, 1st December 2023 00:00 (CET, UTC+1).**
Final speaker confirmation on Friday, 15th December.
-*(We will aim to get a complete list of speakers a week before
-that).*
-
## CFP Introduction
This devroom covers topics mostly related to hardware design
Libre-SOC is a major project in the open-hardware/free-software
space, and will be sharing progress made so far in areas of efficient
-SVP64 assembler, formal verification, and general PowerISA
+SVP64 assembler, formal verification, and general Power ISA
development (proposed advanced biginteger instructions, etc.)
Libre/Open VLSI, very excitingly, has begun to take off, recently.
to the masses.
Please distribute widely to interested parties: anything related to
-VLSI and Open Tape-outs is welcome.
+VLSI and Libre/Open Tape-outs and Silicon development is welcome.
We are looking for any libre or open source topic relating to
hardware design, including but not limited to:
-- Chip Design
+- Chip Design (including nanoscale 3D printing)
- VLSI and FPGA Hardware Design
- Libre/Open Processors in FPGA and/or ASIC
- ISA design and usage
We accept the normal 30 min slot, which gives the speaker about 20-25
-min, and 5 min for Q&A.
+min, and 5 min for Q&A. **NO A LOT MORE TIME IS NEEDED FOR Q&A SEE OHW CFP
+PLUS WE WILL ACCEPT SOME LIGHTNING TALKS**
+
### What is FOSDEM?
FOSDEM 2024 will take place on Saturday 3 and Sunday 4 February 2024.
It will be an in-person event at the **ULB Solbosch Campus, Brussels,
Belgium, Europe.**
-If you aren't there, you can watch the live streams from the main
-tracks and developer rooms.
+If you are unable to attend in-person you can watch any live stream
+from the main tracks and developer rooms.
### Important stuff:
This devroom welcomes anything related to making an ASIC,
or designing one, or using FPGAs, or developing
an FPGA Board, or developing tools and techniques that make VLSI ASIC
-design easier, we'd love to hear from you. Here's a list of topics:
+design easier: we'd love to hear from you. Here's a list of topics:
- Open Hardware projects
- ISA and Architecture design