(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index dd44f4c9cee8b0ebe48ef0e2751506ec64832f07..a278c1ad225d55bc714eab9a355c5c1e91617716 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -116,12 +116,11 @@ CR based predication.  TODO: select alternate CR for twin predication? see [[dis
 
 This is a novel concept that allows predication to be applied to a single source and a single dest register.  The following types of traditional Vector operations may be encoded with it, *without requiring explicit opcodes to do so*
 
-* VSPLAT
-* VEXTRACT
-* VINSERT
-* VREDUCE
-* VEXPAND
-* VCOMPRESS
+* VSPLAT (a single scalar distributed across a vector)
+* VEXTRACT (a single scalar taken from a vector)
+* VINSERT (a scalar inserted into a vector)
+* VREDUCE (sequential selection of certain elements)
+* VEXPAND (insertion of a sequence of elements)
 
 Those patterns (and more) may be applied to:
 
@@ -134,6 +133,8 @@ Those patterns (and more) may be applied to:
 
 This is a huge list that creates extremely powerful combinations, particularly given that one of the predicate options is `(1<<r3)`
 
+Additional unusual capabilities of Twin Predication include a back-to-back version of VREDUCE-VEXPAND which is effectively the ability to do an ordered multiple VINSERT.
+
 # Register Naming
 
 SV Registers are numbered using the notation `SV[F]R<N>_<M>` where `<N>` is a decimal integer and `<M>` is a binary integer. Two integers are used to enable future register expansions to add more registers by appending more LSB bits to `<M>`.