{"vdivuq", VX (4, 11), VX_MASK, POWER10, 0, {VD, VA, VB}},
{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
+{"vstribl", VXVA(4,13,0), VXVA_MASK, POWER10, 0, {VD, VB}},
+{"vstribr", VXVA(4,13,1), VXVA_MASK, POWER10, 0, {VD, VB}},
+{"vstrihl", VXVA(4,13,2), VXVA_MASK, POWER10, 0, {VD, VB}},
+{"vstrihr", VXVA(4,13,3), VXVA_MASK, POWER10, 0, {VD, VB}},
{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"vinsbvlx", VX (4, 15), VX_MASK, POWER10, 0, {VD, RA, VB}},
{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
{"vdivsw", VX (4, 395), VX_MASK, POWER10, 0, {VD, VA, VB}},
{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
+{"vclrlb", VX (4, 397), VX_MASK, POWER10, 0, {VD, VA, RB}},
{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"vinswvrx", VX (4, 399), VX_MASK, POWER10, 0, {VD, RA, VB}},
{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
{"vmulld", VX (4, 457), VX_MASK, POWER10, 0, {VD, VA, VB}},
{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
{"vdivsd", VX (4, 459), VX_MASK, POWER10, 0, {VD, VA, VB}},
+{"vclrrb", VX (4, 461), VX_MASK, POWER10, 0, {VD, VA, RB}},
{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"vinsd", VX (4, 463), VXUIMM4_MASK, POWER10, 0, {VD, RB, UIMM4}},
{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
+{"vstribl.", VXVA(4,1037,0), VXVA_MASK, POWER10, 0, {VD, VB}},
+{"vstribr.", VXVA(4,1037,1), VXVA_MASK, POWER10, 0, {VD, VB}},
+{"vstrihl.", VXVA(4,1037,2), VXVA_MASK, POWER10, 0, {VD, VB}},
+{"vstrihr.", VXVA(4,1037,3), VXVA_MASK, POWER10, 0, {VD, VB}},
{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},