freedreno/a3xx: fix write to bogus register

The loops for updating the multiple packed fields in SP_VS_OUT[] and
SP_VS_VPC_DST[] will zero out one register beyond the last that on
required.  Which is normally not a problem (and is kinda convenient
when looking at cmdstream dumps) unless we have maximum (16) varyings.

Fix loop termination condition so that this does not happen.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_program.c b/src/gallium/drivers/freedreno/a3xx/fd3_program.c
index 2e2a66dc616e474c1b4bb0771ebfc470a82ba80a..17f3dcfe04e455f2461ee8899c7b983f666281c8 100644 (file)
--- a/src/gallium/drivers/freedreno/a3xx/fd3_program.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_program.c
@@ -406,7 +406,7 @@ fd3_program_emit(struct fd_ringbuffer *ring,
                        A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
                        A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(align(fp->total_in, 4) / 4));
 
-       for (i = 0, j = -1; j < (int)fp->inputs_count; i++) {
+       for (i = 0, j = -1; (i < 8) && (j < (int)fp->inputs_count); i++) {
                uint32_t reg = 0;
 
                OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i), 1);
@@ -428,7 +428,7 @@ fd3_program_emit(struct fd_ringbuffer *ring,
                OUT_RING(ring, reg);
        }
 
-       for (i = 0, j = -1; j < (int)fp->inputs_count; i++) {
+       for (i = 0, j = -1; (i < 4) && (j < (int)fp->inputs_count); i++) {
                uint32_t reg = 0;
 
                OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i), 1);