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match up PLL names
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 22 May 2021 11:58:15 +0000
(12:58 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 22 May 2021 11:58:15 +0000
(12:58 +0100)
libresoc/core.py
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diff --git
a/libresoc/core.py
b/libresoc/core.py
index f58a6fba7b4970934dc0ae62ca6094a6fb1b1ef0..35aac19746a0b324d92f0a1dcd15fb64e40243d1 100644
(file)
--- a/
libresoc/core.py
+++ b/
libresoc/core.py
@@
-272,7
+272,7
@@
class LibreSoC(CPU):
if "ls180" in variant and "pll" not in variant:
self.pll_vco_o = Signal()
self.clk_sel = Signal(2)
- self.pll_
ana
_o = Signal()
+ self.pll_
test
_o = Signal()
self.cpu_params['i_clk_sel_i'] = self.clk_sel
self.cpu_params['o_pll_vco_o'] = self.pll_vco_o
self.cpu_params['o_pll_test_o'] = self.pll_test_o