* alpha.c (reg_no_subreg_operand): New function.
* alpha.h (PREDICATE_CODES): Add it.
* alpha.md (floatdi?f patterns): Use it for op1.
From-SVN: r26232
return register_operand (op, mode);
}
-/* Return 1 is OP is a memory location that is not an reference (using
+/* Return 1 is OP is a memory location that is not a reference (using
an AND) to an unaligned location. Take into account what reload
will do. */
return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) != AND;
}
+
+/* Accept a register, but not a subreg of any kind. This allows us to
+ avoid pathological cases in reload wrt data movement common in
+ int->fp conversion. */
+
+int
+reg_no_subreg_operand (op, mode)
+ register rtx op;
+ enum machine_mode mode;
+{
+ if (GET_CODE (op) == SUBREG)
+ return 0;
+ return register_operand (op, mode);
+}
\f
/* Return 1 if this function can directly return via $26. */
{"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
{"any_memory_operand", {MEM}}, \
{"hard_fp_register_operand", {SUBREG, REG}}, \
- {"reg_not_elim_operand", {SUBREG, REG}},
+ {"reg_not_elim_operand", {SUBREG, REG}}, \
+ {"reg_no_subreg_operand", {REG}},
\f
/* Tell collect that the object format is ECOFF. */
#define OBJECT_FORMAT_COFF
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=&f")
- (float:SF (match_operand:DI 1 "register_operand" "f")))]
+ (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
"TARGET_FP && alpha_tp == ALPHA_TP_INSN"
"cvtq%,%+%& %1,%0"
[(set_attr "type" "fadd")
(define_insn "floatdisf2"
[(set (match_operand:SF 0 "register_operand" "=f")
- (float:SF (match_operand:DI 1 "register_operand" "f")))]
+ (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
"TARGET_FP"
"cvtq%,%+%& %1,%0"
[(set_attr "type" "fadd")
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=&f")
- (float:DF (match_operand:DI 1 "register_operand" "f")))]
+ (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
"TARGET_FP && alpha_tp == ALPHA_TP_INSN"
"cvtq%-%+%& %1,%0"
[(set_attr "type" "fadd")
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "register_operand" "=f")
- (float:DF (match_operand:DI 1 "register_operand" "f")))]
+ (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
"TARGET_FP"
"cvtq%-%+%& %1,%0"
[(set_attr "type" "fadd")