arch-arm: Correct target EL field in TLBI operations
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Wed, 10 Apr 2019 13:26:47 +0000 (14:26 +0100)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Thu, 25 Apr 2019 12:48:59 +0000 (12:48 +0000)
Some TLB Invalidation operations affecting the EL2 translation regime
were marked as targeting EL1 instead of EL2

Change-Id: I77821eec7a409e9df6a6814855f9a375832ffe74
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18388
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/isa.cc

index 42e1cba3f0328868b78adbc8364662862d409d62..d5d88e62853b21d2e937770d00c7c719d54df35c 100644 (file)
@@ -1219,7 +1219,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
                 assert32(tc);
                 scr = readMiscReg(MISCREG_SCR, tc);
 
-                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
+                TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
                                 mbits(newVal, 31,12), true);
 
                 tlbiOp(tc);
@@ -1232,7 +1232,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
                 assert32(tc);
                 scr = readMiscReg(MISCREG_SCR, tc);
 
-                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
+                TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
                                 mbits(newVal, 31,12), true);
 
                 tlbiOp.broadcast(tc);
@@ -1347,7 +1347,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
             {
                 assert32(tc);
 
-                TLBIALLN tlbiOp(EL1, true);
+                TLBIALLN tlbiOp(EL2, true);
                 tlbiOp(tc);
                 return;
             }
@@ -1356,7 +1356,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
             {
                 assert32(tc);
 
-                TLBIALLN tlbiOp(EL1, true);
+                TLBIALLN tlbiOp(EL2, true);
                 tlbiOp.broadcast(tc);
                 return;
             }