arch-gcn3: Fix VOP2 dissasembly prints

VOP2 prints VSRC1 register index as hex instead of decimal if the
instruction contains a literal operand.  This patch resets the
format specifiers in the stream to print the register correctly.

Change-Id: Icc7e6588b3c5af545be6590ce412460e72df253f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29936
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

diff --git a/src/arch/gcn3/insts/op_encodings.cc b/src/arch/gcn3/insts/op_encodings.cc
index 2eb4042538ba7818b9302e4bc2b288e695558f0f..fe501f215d1e6620ca64eddce47d87d6ce0165cd 100644 (file)
--- a/src/arch/gcn3/insts/op_encodings.cc
+++ b/src/arch/gcn3/insts/op_encodings.cc
@@ -763,7 +763,8 @@ namespace Gcn3ISA
                        << extData.imm_u32 << ", ";
         }
 
-        dis_stream << "v" << instData.VSRC1;
+        dis_stream << std::resetiosflags(std::ios_base::basefield) << "v"
+            << instData.VSRC1;
 
         if (readsVCC())
             dis_stream << ", vcc";