* [rv64ua/lrsc] Initialize memory read out.
Even though the load contents are discarded, this un-initialized memory value
can lead to a divergence for co-simulation between two different RISC-V designs.
* [rv64ua/lrsc] Use .skip instead of .align.
# TODO is this actually mandatory behavior?
TEST_CASE( 3, a4, 1, \
la a0, foo; \
- add a1, a0, 1024; \
+ la a1, fooTest3; \
lr.w a1, (a1); \
sc.w a4, a1, (a0); \
)
coreid: .word 0
barrier: .word 0
foo: .word 0
+.skip 1024
+fooTest3: .word 0
RVTEST_DATA_END